Saraju P. Mohanty

2009
51	EE	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos: Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO. ACM Great Lakes Symposium on VLSI 2009: 303-308
50	EE	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos: Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments. ISQED 2009: 172-178
49	EE	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra: A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS. ISQED 2009: 47-54
48	EE	Saraju P. Mohanty, Elias Kougianos, Wei Cai, Manish Ratnani: VLSI architectures of perceptual based video watermarking for real-time copyright protection. ISQED 2009: 527-534
47	EE	Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos, Bharat Joshi: A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems. ISQED 2009: 673-679
46	EE	Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan: Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. VLSI Design 2009: 307-312
45	EE	Saraju P. Mohanty: Unified Challenges in Nano-CMOS High-Level Synthesis. VLSI Design 2009: 531
2008
44	EE	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos: A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip. ACM Great Lakes Symposium on VLSI 2008: 47-52
43	EE	Suman Kalyan Mandal, Praveen Bhojwani, Saraju P. Mohanty, Rabi N. Mahapatra: IntellBatt: towards smarter battery design. DAC 2008: 872-877
42	EE	Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan: A nano-CMOS process variation induced read failure tolerant SRAM cell. ISCAS 2008: 3334-3337
41	EE	Saraju P. Mohanty: ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis. ISQED 2008: 174-177
40	EE	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos: A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs. ISQED 2008: 257-260
39	EE	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos: Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design. ISQED 2008: 330-333
38	EE	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. SoCC 2008: 243-246
37	EE	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: Failure analysis for ultra low power nano-CMOS SRAM under process variations. SoCC 2008: 251-254
36	EE	Saraju P. Mohanty, Bharat K. Bhargava: Invisible watermarking based on creation and robust insertion-extraction of image adaptive watermarks. TOMCCAP 5(2): (2008)
2007
35	EE	Elias Kougianos, Saraju P. Mohanty: Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective. VLSI Design 2007: 195-200
34	EE	Saraju P. Mohanty, Elias Kougianos: Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis. VLSI Design 2007: 577-582
2006
33		Saraju P. Mohanty, Anirudha Sahoo: 9th International Conference in Information Technology, ICIT 2006, Bhubaneswar, Orissa, India, 18-21 December 2006 IEEE Computer Society 2006
32	EE	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos: Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits. DATE 2006: 1191-1196
31	EE	Yue Zhuo, Hao Li, Saraju P. Mohanty: A Congestion Driven Placement Algorithm for FPGA Synthesis. FPL 2006: 1-4
30	EE	Saraju P. Mohanty, Elias Kougianos: Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates. ICCD 2006
29	EE	Cheryl A. Kincaid, Saraju P. Mohanty, Armin R. Mikler, Elias Kougianos, Brandon Parker: A High Performance ASIC for Cellular Automata (CA) Applications. ICIT 2006: 289-290
28		Wentong Li, Saraju P. Mohanty, Krishna M. Kavi: A Hardware Assisted High Performance PHK Memory Manager. ISCA PDCS 2006: 229-234
27	EE	Elias Kougianos, Saraju P. Mohanty: Effective tunneling capacitance: a new metric to quantify transient gate leakage current. ISCAS 2006
26	EE	Saraju P. Mohanty, Elias Kougianos, Ramakrishna Velagapudi, Valmiki Mukherjee: Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis. ISCAS 2006
25	EE	Saraju P. Mohanty, Parthasarathy Guturu, Elias Kougianos, Nishikanta Pati: A Novel Invisible Color Image Watermarking Scheme Using Image Adaptive Watermark Creation and Robust Insertion-Extraction. ISM 2006: 153-160
24	EE	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos: Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective. ISQED 2006: 564-569
23	EE	Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mohanty: A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm. VLSI Design 2006: 481-484
22	EE	Saraju P. Mohanty, Elias Kougianos: Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits. VLSI Design 2006: 83-88
21	EE	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: ILP models for simultaneous energy and transient power minimization during behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 11(1): 186-212 (2006)
20	EE	Wentong Li, Saraju P. Mohanty, Krishna M. Kavi: A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator. Computer Architecture Letters 5(2): (2006)
2005
19	EE	Valmiki Mukherjee, Saraju P. Mohanty, Elias Kougianos: A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits. ICCD 2005: 431-437
18	EE	Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki Mukherjee, Hao Li: Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits. ISVLSI 2005: 248-249
17	EE	Saraju P. Mohanty, N. Ranganathan, K. Balakrishnan: Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. VLSI Design 2005: 153-158
16	EE	Saraju P. Mohanty, N. Ranganathan: Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. ACM Trans. Design Autom. Electr. Syst. 10(2): 330-353 (2005)
15	EE	Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa: A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design. IEEE Trans. VLSI Syst. 13(7): 808-818 (2005)
14	EE	Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa: A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*. IEEE Trans. VLSI Syst. 13(8): 1002-1012 (2005)
2004
13	EE	Saraju P. Mohanty, Renuka Kumara C., Sridhara Nayak: FPGA Based Implementation of an Invisible-Robust Image Watermarking Encoder. CIT 2004: 344-353
12	EE	Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa: VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. VLSI Design 2004: 1063-
11	EE	Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi: ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. VLSI Design 2004: 745-748
10	EE	Saraju P. Mohanty, Nagarajan Ranganathan: A framework for energy and transient power reduction during behavioral synthesis. IEEE Trans. VLSI Syst. 12(6): 562-572 (2004)
2003
9	EE	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: Simultaneous peak and average power minimization during datapath scheduling for DSP processors. ACM Great Lakes Symposium on VLSI 2003: 215-220
8	EE	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. ICCD 2003: 441-443
7	EE	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. ISCAS (5) 2003: 313-316
6	EE	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: Peak Power Minimization Through Datapath Scheduling. ISVLSI 2003: 121-126
5	EE	Saraju P. Mohanty, N. Ranganathan: Energy Efficient Scheduling for Datapath Synthesis. VLSI Design 2003: 446-451
4	EE	Saraju P. Mohanty, N. Ranganathan: A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. VLSI Design 2003: 539-545
2002
3	EE	Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna: Datapath Scheduling using Dynamic Frequency Clocking. ISVLSI 2002: 65-70
2000
2		Saraju P. Mohanty, K. R. Ramakrishnan, Mohan S. Kankanhalli: A DCT Domain Visible Watermarking Technique for Images. IEEE International Conference on Multimedia and Expo (II) 2000: 1029-1032
1999
1	EE	Saraju P. Mohanty, K. R. Ramakrishnan, Mohan S. Kankanhalli: A dual watermarking technique for images. ACM Multimedia (2) 1999: 49-51

Coauthor Index

1	K. Balakrishnan	[17]
2	Bharat K. Bhargava	[36]
3	Praveen Bhojwani	[43]
4	Renuka Kumara C.	[13]
5	Wei Cai	[48]
6	Sunil K. Chappidi	[6] [7] [8] [9] [11] [21]
7	Dhruva Ghai	[39] [40] [44] [47] [49] [50] [51]
8	Parthasarathy Guturu	[25]
9	Bharat Joshi	[47]
10	Mohan S. Kankanhalli	[1] [2]
11	Krishna M. Kavi	[20] [28]
12	Cheryl A. Kincaid	[29]
13	Naga M. Kosaraju	[23]
14	Elias Kougianos	[19] [22] [24] [25] [26] [27] [29] [30] [32] [34] [35] [39] [40] [44] [47] [48] [49] [50] [51]
15	Vamsi Krishna	[3]
16	Hao Li	[18] [31]
17	Wentong Li	[20] [28]
18	Rabi N. Mahapatra	[43]
19	Suman Kalyan Mandal	[43]
20	Jimson Mathew	[37] [38] [42] [46]
21	Armin R. Mikler	[29]
22	Valmiki Mukherjee	[18] [19] [26]
23	Ravi Namballa	[12] [14] [15]
24	Sridhara Nayak	[13]
25	Brandon Parker	[29]
26	Nishikanta Pati	[25]
27	Priyadarsan Patra	[49]
28	Dhiraj K. Pradhan	[37] [38] [42] [46]
29	K. R. Ramakrishnan	[1] [2]
30	N. Ranganathan (Nagarajan Ranganathan)	[3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] [15] [16] [17] [21]
31	Manish Ratnani	[48]
32	Anirudha Sahoo	[33]
33	Jawar Singh	[37] [38] [42] [46]
34	Murali R. Varanasi	[23]
35	Ramakrishna Velagapudi	[18] [24] [26] [32]
36	Yue Zhuo	[31]

Colors in the list of coauthors