Dinesh Bhatia

2008
52	EE	Shilpa Bhoj, Dinesh Bhatia: A dynamic temperature control simulation system for FPGAs. FPL 2008: 659-662
51	EE	Shilpa Bhoj, Dinesh Bhatia: Early stage FPGA interconnect leakage power estimation. ICCD 2008: 438-443
50	EE	A. L. Praveen Aroul, Achutan Manohar, Dinesh Bhatia, Leonardo Estevez: Power efficient multi-band contextual activity monitoring for assistive environments. PETRA 2008: 19
2007
49	EE	Shilpa Bhoj, Dinesh Bhatia: Pre-route Interconnect Capacitance and Power Estimation in FPGAs. FPL 2007: 159-164
48	EE	Shilpa Bhoj, Dinesh Bhatia: Thermal Modeling and Temperature Driven Placement for FPGAs. ISCAS 2007: 1053-1056
47	EE	Abhiman Hande, Todd Polk, William Walker, Dinesh Bhatia: Indoor solar energy harvesting for sensor network router nodes. Microprocessors and Microsystems 31(6): 420-432 (2007)
2006
46	EE	Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara: Generic Network Interfaces for Plug and Play NoC Based Architecture. ARC 2006: 287-298
45	EE	Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara: Exploring Logic Block Granularity in Leakage Tolerant FPGA. VLSI Design 2006: 754-757
2005
44	EE	Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia: Exploiting temporal idleness to reduce leakage power in programmable architectures. ASP-DAC 2005: 651-656
43		Shankar Balachandran, Dinesh Bhatia: Timing Aware Interconnect Prediction Models for FPGAs. FPL 2005: 167-172
42		Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara: FPGA Architecture for Standby Power Management. FPT 2005: 181-188
41	EE	Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara: Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA. IPDPS 2005
40	EE	Shankar Balachandran, Dinesh Bhatia: A priori wirelength and interconnect estimation based on circuit characteristic. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1054-1065 (2005)
39	EE	Manjunath Gangadhar, Dinesh Bhatia: FPGA based EBCOT architecture for JPEG 2000. Microprocessors and Microsystems 29(8-9): 363-373 (2005)
2004
38	EE	PariVallal Kannan, Dinesh Bhatia: Estimating Pre-Placement FPGA Interconnection Requirements. VLSI Design 2004: 869-
37		PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia: On metrics for comparing interconnect estimation methods for FPGAs. IEEE Trans. VLSI Syst. 12(4): 381-385 (2004)
2003
36	EE	PariVallal Kannan, Dinesh Bhatia: Interconnect Estimation for FPGAs under Timing Driven Domains. ICCD 2003: 344-349
35	EE	Shankar Balachandran, Dinesh Bhatia: A-priori wirelength and interconnect estimation based on circuit characteristics. SLIP 2003: 77-84
34		John M. Emmert, Sandeep Lodha, Dinesh Bhatia: On Using Tabu Search for Design Automation of VLSI Systems. J. Heuristics 9(1): 75-90 (2003)
2002
33	EE	PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia: On metrics for comparing routability estimation methods for FPGAs. DAC 2002: 70-75
32	EE	PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia: Rapid and Reliable Routability Estimation for FPGAs. FPL 2002: 242-252
31	EE	Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia: On Routing Demand and Congestion Estimation for FPGAs. VLSI Design 2002: 639-646
2001
30	EE	PariVallal Kannan, Dinesh Bhatia: Tightly Integrated Placement and Routing for FPGAs. FPL 2001: 233-242
29	EE	PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia: fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. FPL 2001: 37-47
2000
28	EE	Dinesh Bhatia, James Haralambides: Resource requirements and layouts for field programmable interconnection chips. IEEE Trans. VLSI Syst. 8(3): 346-355 (2000)
27	EE	Dinesh Bhatia, James Haralambides: Bounds, designs and layouts for multi-terminal FPIC architectures. Integration 28(2): 141-156 (2000)
1999
26	EE	John M. Emmert, Dinesh Bhatia: A Methodology for Fast FPGA Floorplanning. FPGA 1999: 47-56
25		Dinesh Bhatia, Kuldeep S. Simha, PariVallal Kannan: NEBULA: A Partially and Dynamically Reconfigurable Architecture. FPL 1999: 405-410
24		John M. Emmert, Dinesh Bhatia: Tabu Search: Ultra-Fast Placement for FPGAs. FPL 1999: 81-90
23	EE	John M. Emmert, Dinesh Bhatia: Fast timing driven placement using tabu search. ISCAS (1) 1999: 302-305
22	EE	Gregory Tumbush, Dinesh Bhatia: Clustering to improve bi-partition quality and run time. ISCAS (6) 1999: 145-148
21		Karthikeya M. Gajjala Purna, Dinesh Bhatia: Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers. IEEE Trans. Computers 48(6): 579-590 (1999)
1998
20	EE	Karthikeya M. Gajjala Purna, Dinesh Bhatia: Temporal Partitioning and Scheduling for Reconfigurable Computing. FCCM 1998: 329-330
19	EE	John M. Emmert, Akash Randhar, Dinesh Bhatia: Fast Floorplanning for FPGAs. FPL 1998: 129-138
18	EE	Dinesh Bhatia, PariVallal Kannan, Kuldeep S. Simha, Karthikeya M. Gajjala Purna: REACT: Reactive Environment for Runtime Reconfiguration. FPL 1998: 209-217
17	EE	Karthikeya M. Gajjala Purna, Dinesh Bhatia: Emulating Large Designs on Small Reconfigurable Hardware. International Workshop on Rapid System Prototyping 1998: 58-63
16	EE	Raghu Burra, Dinesh Bhatia: Timing Driven Multi-FPGA Board Partitioning. VLSI Design 1998: 234-
1997
15	EE	Jianzhong Shi, Dinesh Bhatia: Performance Driven Floorplanning for FPGA Based Designs. FPGA 1997: 112-118
14		John M. Emmert, Dinesh Bhatia: Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. FPL 1997: 141-150
13		Gregory Tumbush, Dinesh Bhatia: Partitioning Under Timing and Area Constraints. ICCD 1997: 614-620
12	EE	Jianzhong Shi, Akash Randhar, Dinesh Bhatia: Macro Block Based FPGA Floorplanning. VLSI Design 1997: 21-26
11	EE	Dinesh Bhatia: Reconfigurable Computing. VLSI Design 1997: 356-359
1996
10		Doug Smith, Dinesh Bhatia: RACE: Reconfigurable and Adaptive Computing Environment. FPL 1996: 87-95
9	EE	Vijayanand Sankarasubramanian, Dinesh Bhatia: Multiway Partitioner for High Performance FPGA Based Board Architecture. ICCD 1996: 579-
8	EE	Natesan Venkateswaran, Dinesh Bhatia: Clock-Skew Constrained Cell Placement. VLSI Design 1996: 146-149
1995
7	EE	Dinesh Bhatia, James Haralambides: Resource requirements for field programmable interconnection chips. VLSI Design 1995: 376-380
6	EE	Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia: Pseudo-exhaustive built-in TPG for sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1160-1171 (1995)
1994
5		Amit Chowdhary, Dinesh Bhatia: Detailed Routing of Multi-Terminal Nets in FPGAs. VLSI Design 1994: 237-242
4		Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori: Hierarchical Reconfiguration of VLSI/WSI Arrays. VLSI Design 1994: 349-352
1993
3		Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia: Pseudoexhaustive BIST for Sequential Circuits. ICCD 1993: 523-527
1992
2		Dinesh Bhatia, Frank Thomson Leighton, Fillia Makedon, Carolyn Haibt Norton: Improved Algorithms for Routing on Two-Dimensional Grids. WG 1992: 114-122
1990
1		Dinesh Bhatia, Frank Thomson Leighton, Fillia Makedon: Efficient Reconfiguration of WSI Arrays. ICSI 1990: 47-56

Coauthor Index

1	A. L. Praveen Aroul	[50]
2	Shankar Balachandran	[29] [31] [32] [33] [35] [37] [40] [43]
3	Dheera Balasubramanian	[46]
4	Poras T. Balsara	[41] [42] [44] [45] [46]
5	Rajarshee P. Bharadwaj	[42] [44] [45]
6	Shilpa Bhoj	[46] [48] [49] [51] [52]
7	Raghu Burra	[16]
8	Amit Chowdhary	[5]
9	Mukesh Chugh	[41]
10	John M. Emmert	[14] [19] [23] [24] [26] [34]
11	Leonardo Estevez	[50]
12	Manjunath Gangadhar	[39]
13	Abhiman Hande	[47]
14	James Haralambides	[7] [27] [28]
15	Dimitrios Kagaris (Dimitri Kagaris)	[3] [6]
16	PariVallal Kannan	[18] [25] [29] [30] [31] [32] [33] [36] [37] [38]
17	Srinivas Katkoori	[4]
18	Rajan Konar	[42] [44] [45]
19	Frank Thomson Leighton (Tom Leighton)	[1] [2]
20	Sandeep Lodha	[34]
21	Fillia Makedon	[1] [2]
22	Achutan Manohar	[50]
23	Tanvi Nagda	[46]
24	Carolyn Haibt Norton	[2]
25	Todd Polk	[47]
26	Karthikeya M. Gajjala Purna	[17] [18] [20] [21]
27	Ramesh Rajagopalan	[4]
28	Akash Randhar	[12] [19]
29	Vijayanand Sankarasubramanian	[9]
30	Jianzhong Shi	[12] [15]
31	Kuldeep S. Simha	[18] [25]
32	Sanjay Pratap Singh	[46]
33	Doug Smith	[10]
34	Spyros Tragoudas	[3] [6]
35	Gregory Tumbush	[13] [22]
36	Natesan Venkateswaran	[8]
37	William Walker	[47]

Colors in the list of coauthors