Poras T. Balsara

2007
40	EE	Chitranjan K. Singh, Naofal Al-Dhahir, Poras T. Balsara: Effect of Word-length Precision on the Performance of MIMO Systems. ISCAS 2007: 2598-2601
39	EE	Viral K. Parikh, Poras T. Balsara, Oren Eliezer, Jaimin Mehta: A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters. ISCAS 2007: 3275-3278
38	EE	Viral K. Parikh, Poras T. Balsara, Oren Eliezer, Jaimin Mehta: A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters. ISCAS 2007: 3279-3282
37	EE	Chitranjan K. Singh, Sushma Honnavara Prasad, Poras T. Balsara: VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition. VLSI Design 2007: 836-841
36	EE	Raghunath Cherukuri, Poras T. Balsara: Iterative (TURBO) IQ Imbalance Estimation and Correction in BICM-ID for Flat Fading Channels. VTC Fall 2007: 2070-2074
2006
35	EE	Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara: Generic Network Interfaces for Plug and Play NoC Based Architecture. ARC 2006: 287-298
34	EE	Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara: Reconfigurable CAM Architecture for Network Search Engines. ICCD 2006
33	EE	I. L. Syllaios, Poras T. Balsara, O. E. Eliezer: A generalized signal reconstruction method for designing interpolation filters. ISCAS 2006
32	EE	V. Ramakrishnan, Poras T. Balsara: A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter. VLSI Design 2006: 197-202
31	EE	Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara: Exploring Logic Block Granularity in Leakage Tolerant FPGA. VLSI Design 2006: 754-757
2005
30	EE	Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia: Exploiting temporal idleness to reduce leakage power in programmable architectures. ASP-DAC 2005: 651-656
29		Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara: FPGA Architecture for Standby Power Management. FPT 2005: 181-188
28	EE	Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara: Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines. ICCD 2005: 243-248
27	EE	Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara: Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA. IPDPS 2005
26	EE	Robert B. Staszewski, Roman Staszewski, Poras T. Balsara: VHDL Simulation and Modeling of an All-Digital RF Transmitter. IWSOC 2005: 233-238
25	EE	N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell: The Impact of Inductance on Transients Affecting Gate Oxide Reliability. VLSI Design 2005: 709-713
24	EE	Ramaprasath Vilangudipitchai, Poras T. Balsara: Power Switch Network Design for MTCMOS. VLSI Design 2005: 836-839
23	EE	Robert B. Staszewski, Roman Staszewski, John L. Wallberg, Tom Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, K. Maggio, Poras T. Balsara: SoC with an integrated DSP and a 2.4-GHz RF transmitter. IEEE Trans. VLSI Syst. 13(11): 1253-1265 (2005)
2004
22	EE	Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara: PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks. ICCD 2004: 6-11
21		Robert B. Staszewski, Chan Fernando, Poras T. Balsara: Event-driven simulation and modeling of an RF oscillator. ISCAS (4) 2004: 641-644
20	EE	N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara: Interconnect Modeling for Copper/Low-k Technologies. VLSI Design 2004: 425-
2003
19	EE	N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell: Benchmarks for Interconnect Parasitic Resistance and Capacitance. ISQED 2003: 163-
2002
18	EE	N. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell: Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. VLSI Design 2002: 141
2001
17	EE	Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara: Challenges in integrated CMOS transceivers for short distance wireless. ACM Great Lakes Symposium on VLSI 2001: 45-50
16	EE	Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell: Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. VLSI Design 2001: 365-370
15	EE	Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara: Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels. IEEE Trans. VLSI Syst. 9(1): 42-51 (2001)
2000
14	EE	Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley: Reconfigurable Array Media Processor (RAMP). FCCM 2000: 287-288
13	EE	Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara: Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels. ISLPED 2000: 262-267
12	EE	Uming Ko, Poras T. Balsara: High-performance energy-efficient D-flip-flop circuits. IEEE Trans. VLSI Syst. 8(1): 94-98 (2000)
1999
11		Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell: Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis. VLSI Design 1999: 6-11
10	EE	Shivaling S. Mahant-Shetti, Poras T. Balsara, Carl Lemonds: High performance low power array multiplier using temporal tiling. IEEE Trans. VLSI Syst. 7(1): 121-124 (1999)
1998
9		Sharat Prasad, Kamran Kiasaleh, Poras T. Balsara: LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service. INFOCOM 1998: 174-182
8	EE	Uming Ko, Poras T. Balsara, Ashwini K. Nanda: Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. VLSI Syst. 6(2): 299-308 (1998)
1996
7	EE	Shivaling S. Mahant-Shetti, Carl Lemonds, Poras T. Balsara: Leap frog multiplier. ISLPED 1996: 221-223
6	EE	Uming Ko, Anthony M. Hill, Poras T. Balsara: Design techniques for high performance, energy efficient control logic. ISLPED 1996: 97-100
1995
5	EE	Uming Ko, Poras T. Balsara, Ashwini K. Nanda: Energy optimization of multi-level processor cache architectures. ISLPD 1995: 45-49
4	EE	M. Agarwala, Poras T. Balsara: An architecture for a DSP field-programmable gate array. IEEE Trans. VLSI Syst. 3(1): 136-141 (1995)
3	EE	Uming Ko, Poras T. Balsara: Short-circuit power driven gate sizing technique for reducing power dissipation. IEEE Trans. VLSI Syst. 3(3): 450-455 (1995)
1991
2		Poras T. Balsara, Robert Michael Owens, Mary Jane Irwin: Digit Serial Multipliers. J. Parallel Distrib. Comput. 11(2): 156-162 (1991)
1	EE	Poras T. Balsara, Mary Jane Irwin: Image processing on a memory array architecture. VLSI Signal Processing 2(4): 313-324 (1991)

Coauthor Index

1	M. Agarwala	[4]
2	Mohammad J. Akhbarizadeh	[22] [28]
3	Naofal Al-Dhahir	[40]
4	Dheera Balasubramanian	[35]
5	Rajarshee P. Bharadwaj	[29] [30] [31]
6	Dinesh Bhatia	[27] [29] [30] [31] [35]
7	Shilpa Bhoj	[35]
8	Tom Bonifield	[19] [20]
9	Frank Cano	[19]
10	Cyrus D. Cantrell	[11] [16] [18] [19] [25]
11	Raghunath Cherukuri	[36]
12	Mukesh Chugh	[27]
13	O. E. Eliezer	[33]
14	Oren Eliezer	[38] [39]
15	Chan Fernando	[21]
16	Jose Flores	[14]
17	Patrick Friel	[14]
18	Roger Griesmer	[20]
19	Anthony M. Hill	[6]
20	Chih-Ming Hung	[23]
21	William R. Hunter	[25]
22	Mary Jane Irwin	[1] [2]
23	Tom Jung	[23]
24	Kamran Kiasaleh	[9]
25	Uming Ko	[3] [5] [6] [8] [12]
26	Jinseok Koh	[23]
27	Rajan Konar	[29] [30] [31]
28	Mak Kulkarni	[19]
29	Dirk Leipold	[23]
30	Carl Lemonds	[7] [10]
31	K. Maggio	[23]
32	Shivaling S. Mahant-Shetti	[7] [10]
33	Jaimin Mehta	[38] [39]
34	Khurram Muhammad	[13] [15] [17]
35	N. S. Nagaraj	[18] [19] [20] [25]
36	Tanvi Nagda	[35]
37	Ashwini K. Nanda	[5] [8]
38	Usha Narasimha	[19]
39	Mehrdad Nourani	[22] [28] [34]
40	Nagaraj Ns	[11] [16]
41	Robert Michael Owens	[2]
42	Viral K. Parikh	[38] [39]
43	Sharat Prasad	[9]
44	Sushma Honnavara Prasad	[37]
45	V. Ramakrishnan	[32]
46	Kamlesh Rath	[14]
47	Abha Singh	[19] [20]
48	Chitranjan K. Singh	[37] [40]
49	Sanjay Pratap Singh	[35]
50	Robert B. Staszewski	[13] [15] [17] [21] [23] [26]
51	Roman Staszewski	[23] [26]
52	I. L. Syllaios	[33]
53	Sirisha Tangirala	[14]
54	Deepak S. Vijayasarathi	[22] [28] [34]
55	Ramaprasath Vilangudipitchai	[24]
56	John P. Wadley	[14]
57	John L. Wallberg	[23]

Colors in the list of coauthors