Abdelhalim Alsharqawi

2006
6	EE	Rashad Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui: Synthesis of Pipelined SRSL Circuits. ISVLSI 2006: 71-76
5	EE	Abdelhalim Alsharqawi, Abdel Ejnioui: Clockless Pipelining for Coarse Grain Datapaths. VLSI Design 2006: 749-753
2005
4	EE	Abdelhalim Alsharqawi, Abdel Ejnioui: Synthesis of Self-Resetting Stage Logic Pipelines. ISVLSI 2005: 260-262
2004
3	EE	Abdel Ejnioui, Abdelhalim Alsharqawi: Self-resetting stage logic pipelines. ACM Great Lakes Symposium on VLSI 2004: 174-177
2	EE	Abdel Ejnioui, Abdelhalim Alsharqawi: Pipeline-Level Control of Self-Resetting Pipelines. DSD 2004: 342-349
1	EE	Abdel Ejnioui, Abdelhalim Alsharqawi: Pipeline Design Based on Self-Resetting Stage Logic. ISVLSI 2004: 254-257

Coauthor Index

1	Abdel Ejnioui	[1] [2] [3] [4] [5] [6]
2	Rashad Oreifej	[6]