Partha S. Roop

2008
32	EE	Roopak Sinha, Partha S. Roop, Samik Basu: A Module Checking Based Converter Synthesis Approach for SoCs. VLSI Design 2008: 492-501
31	EE	Roopak Sinha, Partha S. Roop, Samik Basu: A Model Checking Approach to Protocol Conversion. Electr. Notes Theor. Comput. Sci. 203(4): 81-94 (2008)
2007
30	EE	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: McCharts and Multiclock FSMs for modeling large scale systems. MEMOCODE 2007: 3-12
29	EE	Samik Basu, Partha S. Roop, Roopak Sinha: Local Module Checking for CTL Specifications. Electr. Notes Theor. Comput. Sci. 176(2): 125-141 (2007)
28	EE	Hai-Feng Guo, Miao Liu, Partha S. Roop, C. R. Ramakrishnan, I. V. Ramakrishnan: Precise specification matching for adaptive reuse in embedded systems. J. Applied Logic 5(2): 333-355 (2007)
2006
27	EE	Flavius Gruian, Partha S. Roop, Zoran A. Salcic, Ivan Radojevic: The SystemJ approach to system-level design. MEMOCODE 2006: 149-158
26	EE	Zoran A. Salcic, Flavius Gruian, Partha S. Roop, Alif Wahid: A Scheduler Support Unit for Reactive Microprocessors. RTCSA 2006: 368-372
25	EE	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation. VLSI Design 2006: 461-464
24	EE	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: Modeling Embedded Systems: From SystemC and Esterel to DFCharts. IEEE Design & Test of Computers 23(5): 348-358 (2006)
23	EE	Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari: HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems. Microprocessors and Microsystems 30(2): 72-85 (2006)
2005
22	EE	Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari: REMIC: design of a reactive embedded microprocessor core. ASP-DAC 2005: 977-981
21	EE	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: Modelling Heterogeneous Embedded Systems in DFCarts. FDL 2005: 441-453
20	EE	Robi Malik, Partha S. Roop: Adaptive Techniques for Specification Matching in Embedded Systems: A Comparative Study. IFM 2005: 33-52
19	EE	Roopak Sinha, Partha S. Roop, Bakhadyr Khoussainov: Adaptive Verification using Forced Simulation. Electr. Notes Theor. Comput. Sci. 141(3): 171-197 (2005)
18	EE	Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: A New Model for Heterogeneous Embedded Systems - What Esterel and SyncCharts Need to Become a Suitable Specification Platform. International Journal of Software Engineering and Knowledge Engineering 15(2): 405-410 (2005)
2004
17	EE	Partha S. Roop, Zoran A. Salcic, M. W. Sajeewa Dayaratne: Towards direct execution of esterel programs on reactive processors. EMSOFT 2004: 240-248
16		Zoran A. Salcic, Partha S. Roop: Customizing Processor Cores to Support Reactivity. ERSA 2004: 194-202
15		Zoran A. Salcic, Partha S. Roop, Dong Hui, Ivan Radojevic: HiDRA: A New Architecture for Heterogeneous Embedded Systems. ESA/VLSI 2004: 164-170
14	EE	Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli: REFLIX: a processor core with native support for control-dominated embedded applications. Microprocessors and Microsystems 28(1): 13-25 (2004)
2003
13	EE	Partha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli: A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems. VLSI Design 2003: 189-194
12	EE	Rick Mugridge, Bruce MacDonald, Partha S. Roop: A Customer Test Generator for Web-Based Systems. XP 2003: 189-197
11	EE	Rick Mugridge, Bruce MacDonald, Partha S. Roop, Ewan D. Tempero: Five Challenges in Teaching XP. XP 2003: 406-409
2002
10	EE	Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli: REFLIX: A Processor Core for Reactive Embedded Applications. FPL 2002: 945-945
9	EE	Partha S. Roop, Arcot Sowmya, S. Ramesh: k-time Forced Simulation: A Formal Verification Technique for IP Reuse. ICCD 2002: 50-55
2001
8	EE	Partha S. Roop, Arcot Sowmya, S. Ramesh: A formal approach to component based development of synchronous programs. ASP-DAC 2001: 421-424
7	EE	Partha S. Roop, Arcot Sowmya, S. Ramesh: Forced simulation: A technique for automating component reuse in embedded systems. ACM Trans. Design Autom. Electr. Syst. 6(4): 602-628 (2001)
2000
6	EE	Partha S. Roop, Arcot Sowmya, S. Ramesh: Automated Component Adaptation by Forced Simulation. ACAC 2000: 74-81
5	EE	Partha S. Roop, Arcot Sowmya, S. Ramesh: Automatic Component Matching Using Forced Simulation. VLSI Design 2000: 64-69
1998
4	EE	Partha S. Roop, Arcot Sowmya: Hidden time model for specification and verification of embedded systems. ECRTS 1998: 98-105
3	EE	Partha S. Roop, Arcot Sowmya: CFSMcharts: A New Language for Microprocessor Based system Design. VLSI Design 1998: 342-346
1996
2	EE	Raj S. Mitra, Partha S. Roop, Anupam Basu: A new algorithm for implementation of design functions by available devices. IEEE Trans. VLSI Syst. 4(2): 170-180 (1996)
1995
1	EE	Raj S. Mitra, Partha S. Roop, Anupam Basu: Implementation of design functions by available devices: a new algorithm. VLSI Design 1995: 30-35

Coauthor Index

1	Anupam Basu	[1] [2]
2	Samik Basu	[29] [31] [32]
3	Abbas Bigdeli	[10] [13] [14]
4	Morteza Biglari-Abhari	[10] [13] [14] [22] [23]
5	M. W. Sajeewa Dayaratne	[17]
6	Flavius Gruian	[26] [27]
7	Hai-Feng Guo	[28]
8	Dong Hui	[15] [22] [23]
9	Bakhadyr Khoussainov	[19]
10	Miao Liu	[28]
11	Bruce MacDonald	[11] [12]
12	Robi Malik	[20]
13	Raj S. Mitra	[1] [2]
14	Rick Mugridge	[11] [12]
15	Ivan Radojevic	[15] [18] [21] [24] [25] [27] [30]
16	C. R. Ramakrishnan	[28]
17	I. V. Ramakrishnan	[28]
18	S. Ramesh (Sethu Ramesh)	[5] [6] [7] [8] [9]
19	Zoran A. Salcic	[10] [13] [14] [15] [16] [17] [18] [21] [22] [23] [24] [25] [26] [27] [30]
20	Roopak Sinha	[19] [29] [31] [32]
21	Arcot Sowmya	[3] [4] [5] [6] [7] [8] [9]
22	Ewan D. Tempero	[11]
23	Alif Wahid	[26]

Colors in the list of coauthors