| 2006 |
|---|
| 6 | EE | Koushik K. Das,
Shih-Hsien Lo,
Ching-Te Chuang:
High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header.
VLSI Design 2006: 758-761 |
| 5 | EE | Scott Hanson,
Bo Zhai,
Kerry Bernstein,
David Blaauw,
Andres Bryant,
Leland Chang,
Koushik K. Das,
Wilfried Haensch,
Edward J. Nowak,
Dennis Sylvester:
Ultralow-voltage, minimum-energy CMOS.
IBM Journal of Research and Development 50(4-5): 469-490 (2006) |
| 2004 |
|---|
| 4 | EE | Keunwoo Kim,
Koushik K. Das,
Rajiv V. Joshi,
Ching-Te Chuang:
Nanoscale CMOS circuit leakage power reduction by double-gate device.
ISLPED 2004: 102-107 |
| 2003 |
|---|
| 3 | EE | Koushik K. Das,
Rajiv V. Joshi,
Ching-Te Chuang,
Peter W. Cook,
Richard B. Brown:
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology.
ISLPED 2003: 168-171 |
| 2 | EE | Koushik K. Das,
Richard B. Brown:
Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS.
ISVLSI 2003: 29-34 |
| 1 | EE | Koushik K. Das,
Richard B. Brown:
Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology.
VLSI Design 2003: 291-296 |
