H. Udayakumar

2009
13	EE	Parimala Viswanath, Pranav Murthy, Debajit Das, R. Venkatraman, Ajoy Mandal, Arvind Veeravalli, H. Udayakumar: Optimization strategies to improve statistical timing. ISQED 2009: 476-481
12	EE	Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao: Clock gating effectiveness metrics: Applications to power optimization. ISQED 2009: 482-487
11	EE	Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind: An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis. VLSI Design 2009: 519-524
2008
10	EE	Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao: Clock gating for power optimization in ASIC design cycle theory & practice. ISLPED 2008: 307-308
9	EE	Sukumar Jairam, S. M. Stalin, Jean-Yves Oberle, H. Udayakumar: An SSO Based Methodology for EM Emission Estimation from SoCs. ISQED 2008: 297-300
8	EE	Ajit Gupte, Mohit Sharma, Gaurav Varshney, Lakshmikantha Holla, Parvinder Rana, H. Udayakumar: Memory Power Modeling - A Novel Approach. ISVLSI 2008: 263-268
2006
7	EE	Snehashis Roy, Sukumar Jairam, H. Udayakumar: A Methodology for Switching Activity Based IO Powerpad Optimisation. VLSI Design 2006: 794-797
2005
6	EE	Sankar P. Debnath, Sukumar Jairam, H. Udayakumar: A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses. VLSI Design 2005: 808-811
2004
5	EE	P. R. Suresh, P. K. Sundararajan, Anshuli Goel, H. Udayakumar, C. Srinivasan, Vasudev Sinari, Raghavendrakumar Ravinutala: Package-silicon co-design - Experiment with an SOC design. VLSI Design 2004: 531-
2002
4	EE	Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji: Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. VLSI Design 2002: 781-788
2000
3	EE	Karthikeyan Madathil, Jagdish C. Rao, Subash G. Chandar, Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar: A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. VLSI Design 2000: 468-
1999
2	EE	Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash G. Chandar: A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. ICCD 1999: 340-347
1	EE	Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar: A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors. VLSI Design 1999: 346-349

Coauthor Index

1	Jais Abraham	[4]
2	N. V. Arvind	[11]
3	Amit M. Brahme	[3]
4	Subash G. Chandar	[2] [3]
5	Debajit Das	[13]
6	Sankar P. Debnath	[6]
7	Avinash K. Gautam	[1] [2] [3]
8	Anshuli Goel	[5]
9	Ajit Gupte	[8]
10	Lakshmikantha Holla	[8]
11	Shyam S. Jagini	[4]
12	Sukumar Jairam	[6] [7] [9] [10] [12]
13	Karthikeyan Madathil	[2] [3]
14	Ajoy Mandal	[13]
15	Amitabh Menon	[2] [3]
16	Parag Mhatre	[4]
17	Pranav Murthy	[13]
18	Jean-Yves Oberle	[9]
19	Rubin A. Parekhji	[4]
20	Parvinder Rana	[8]
21	Jagdish C. Rao	[1] [2] [3] [4] [10] [12]
22	Madhusudan Rao	[10] [12]
23	Rohit Rathi	[1]
24	Raghavendrakumar Ravinutala	[5]
25	Snehashis Roy	[7]
26	M. Sambandam	[4]
27	Soujanna Sarkar	[4]
28	Vilesh Shah	[2]
29	Karanth Shankaranarayana	[4]
30	Mohit Sharma	[8]
31	K. P. Sheshadri	[4]
32	Vasudev Sinari	[5]
33	Jithendra Srinivas	[10] [12]
34	C. Srinivasan	[5]
35	S. M. Stalin	[9]
36	P. K. Sundararajan	[5]
37	P. R. Suresh	[5]
38	S. Talapatra	[4]
39	Gaurav Varshney	[8]
40	Arvind Veeravalli	[13]
41	N. Venkatesh	[4]
42	R. Venkatraman	[4] [13]
43	Ramakrishnan Venkatraman	[11]
44	Parimala Vishwanath	[10]
45	Ramamurthy Vishweshwara	[11]
46	Parimala Viswanath	[13]

Colors in the list of coauthors