2009 |
13 | EE | Parimala Viswanath,
Pranav Murthy,
Debajit Das,
R. Venkatraman,
Ajoy Mandal,
Arvind Veeravalli,
H. Udayakumar:
Optimization strategies to improve statistical timing.
ISQED 2009: 476-481 |
12 | EE | Jithendra Srinivas,
Madhusudan Rao,
Sukumar Jairam,
H. Udayakumar,
Jagdish C. Rao:
Clock gating effectiveness metrics: Applications to power optimization.
ISQED 2009: 482-487 |
11 | EE | Ramamurthy Vishweshwara,
Ramakrishnan Venkatraman,
H. Udayakumar,
N. V. Arvind:
An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis.
VLSI Design 2009: 519-524 |
2008 |
10 | EE | Sukumar Jairam,
Madhusudan Rao,
Jithendra Srinivas,
Parimala Vishwanath,
H. Udayakumar,
Jagdish C. Rao:
Clock gating for power optimization in ASIC design cycle theory & practice.
ISLPED 2008: 307-308 |
9 | EE | Sukumar Jairam,
S. M. Stalin,
Jean-Yves Oberle,
H. Udayakumar:
An SSO Based Methodology for EM Emission Estimation from SoCs.
ISQED 2008: 297-300 |
8 | EE | Ajit Gupte,
Mohit Sharma,
Gaurav Varshney,
Lakshmikantha Holla,
Parvinder Rana,
H. Udayakumar:
Memory Power Modeling - A Novel Approach.
ISVLSI 2008: 263-268 |
2006 |
7 | EE | Snehashis Roy,
Sukumar Jairam,
H. Udayakumar:
A Methodology for Switching Activity Based IO Powerpad Optimisation.
VLSI Design 2006: 794-797 |
2005 |
6 | EE | Sankar P. Debnath,
Sukumar Jairam,
H. Udayakumar:
A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses.
VLSI Design 2005: 808-811 |
2004 |
5 | EE | P. R. Suresh,
P. K. Sundararajan,
Anshuli Goel,
H. Udayakumar,
C. Srinivasan,
Vasudev Sinari,
Raghavendrakumar Ravinutala:
Package-silicon co-design - Experiment with an SOC design.
VLSI Design 2004: 531- |
2002 |
4 | EE | Karanth Shankaranarayana,
Soujanna Sarkar,
R. Venkatraman,
Shyam S. Jagini,
N. Venkatesh,
Jagdish C. Rao,
H. Udayakumar,
M. Sambandam,
K. P. Sheshadri,
S. Talapatra,
Parag Mhatre,
Jais Abraham,
Rubin A. Parekhji:
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.
VLSI Design 2002: 781-788 |
2000 |
3 | EE | Karthikeyan Madathil,
Jagdish C. Rao,
Subash G. Chandar,
Amitabh Menon,
Avinash K. Gautam,
Amit M. Brahme,
H. Udayakumar:
A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores.
VLSI Design 2000: 468- |
1999 |
2 | EE | Avinash K. Gautam,
Jagdish C. Rao,
Karthikeyan Madathil,
Vilesh Shah,
H. Udayakumar,
Amitabh Menon,
Subash G. Chandar:
A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology.
ICCD 1999: 340-347 |
1 | EE | Avinash K. Gautam,
Jagdish C. Rao,
Rohit Rathi,
H. Udayakumar:
A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors.
VLSI Design 1999: 346-349 |