Elias Kougianos

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19EEDhruva Ghai, Saraju P. Mohanty, Elias Kougianos: Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO. ACM Great Lakes Symposium on VLSI 2009: 303-308
18EEDhruva Ghai, Saraju P. Mohanty, Elias Kougianos: Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments. ISQED 2009: 172-178
17EEDhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra: A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS. ISQED 2009: 47-54
16EESaraju P. Mohanty, Elias Kougianos, Wei Cai, Manish Ratnani: VLSI architectures of perceptual based video watermarking for real-time copyright protection. ISQED 2009: 527-534
15EESaraju P. Mohanty, Dhruva Ghai, Elias Kougianos, Bharat Joshi: A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems. ISQED 2009: 673-679
14EEDhruva Ghai, Saraju P. Mohanty, Elias Kougianos: A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip. ACM Great Lakes Symposium on VLSI 2008: 47-52
13EEDhruva Ghai, Saraju P. Mohanty, Elias Kougianos: A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs. ISQED 2008: 257-260
12EEDhruva Ghai, Saraju P. Mohanty, Elias Kougianos: Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design. ISQED 2008: 330-333
11EEElias Kougianos, Saraju P. Mohanty: Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective. VLSI Design 2007: 195-200
10EESaraju P. Mohanty, Elias Kougianos: Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis. VLSI Design 2007: 577-582
9EESaraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos: Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits. DATE 2006: 1191-1196
8EESaraju P. Mohanty, Elias Kougianos: Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates. ICCD 2006
7EECheryl A. Kincaid, Saraju P. Mohanty, Armin R. Mikler, Elias Kougianos, Brandon Parker: A High Performance ASIC for Cellular Automata (CA) Applications. ICIT 2006: 289-290
6EEElias Kougianos, Saraju P. Mohanty: Effective tunneling capacitance: a new metric to quantify transient gate leakage current. ISCAS 2006
5EESaraju P. Mohanty, Elias Kougianos, Ramakrishna Velagapudi, Valmiki Mukherjee: Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis. ISCAS 2006
4EESaraju P. Mohanty, Parthasarathy Guturu, Elias Kougianos, Nishikanta Pati: A Novel Invisible Color Image Watermarking Scheme Using Image Adaptive Watermark Creation and Robust Insertion-Extraction. ISM 2006: 153-160
3EESaraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos: Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective. ISQED 2006: 564-569
2EESaraju P. Mohanty, Elias Kougianos: Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits. VLSI Design 2006: 83-88
1EEValmiki Mukherjee, Saraju P. Mohanty, Elias Kougianos: A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits. ICCD 2005: 431-437

Coauthor Index

1Wei Cai [16]
2Dhruva Ghai [12] [13] [14] [15] [17] [18] [19]
3Parthasarathy Guturu [4]
4Bharat Joshi [15]
5Cheryl A. Kincaid [7]
6Armin R. Mikler [7]
7Saraju P. Mohanty [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
8Valmiki Mukherjee [1] [5]
9Brandon Parker [7]
10Nishikanta Pati [4]
11Priyadarsan Patra [17]
12Manish Ratnani [16]
13Ramakrishna Velagapudi [3] [5] [9]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)