| |
| 2007 | ||
|---|---|---|
| 4 | EE | Gaurav Trivedi, H. Narayanan: Application of Fast DC Analysis to Partitioning Hypergraphs. ISCAS 2007: 3407-3410 |
| 3 | EE | Gaurav Trivedi, Madhav P. Desai, H. Narayanan: Parallelization of DC Analysis through Multiport Decomposition. VLSI Design 2007: 863-868 |
| 2 | EE | Gaurav Trivedi, Sumit Punglia, H. Narayanan: Application of DC Analyzer to Combinatorial Optimization Problems. VLSI Design 2007: 869-874 |
| 2006 | ||
| 1 | EE | Gaurav Trivedi, Madhav P. Desai, H. Narayanan: Fast DC Analysis and Its Application to Combinatorial Optimization Problems. VLSI Design 2006: 695-700 |
| 1 | Madhav P. Desai | [1] [3] |
| 2 | H. Narayanan | [1] [2] [3] [4] |
| 3 | Sumit Punglia | [2] |