| 2006 |
|---|
| 7 | EE | Jin-Tai Yan,
Yen-Hsiang Chen,
Chia-Fang Lee,
Ming-Ching Huang:
Multilevel timing-constrained full-chip routing in hierarchical quad-grid model.
ISCAS 2006 |
| 6 | EE | Jin-Tai Yan,
Kuen-Ming Lin,
Yen-Hsiang Chen:
Optimal shielding insertion for inductive noise avoidance.
ISCAS 2006 |
| 5 | EE | Jin-Tai Yan,
Chia-Fang Lee,
Yen-Hsiang Chen:
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing.
VLSI Design 2006: 147-152 |
| 2005 |
|---|
| 4 | EE | Jin-Tai Yan,
Yen-Hsiang Chen,
Chia-Wei Wu:
Probabilistic congestion prediction in hierarchical quad-grid model.
ISCAS (2) 2005: 1350-1353 |
| 3 | EE | Jin-Tai Yan,
Chia-Wei Wu,
Yen-Hsiang Chen:
Wiring area optimization in floorplan-aware hierarchical power grids.
ISCAS (2) 2005: 1366-1369 |
| 2 | EE | Jin-Tai Yan,
Kai-Ping Lin,
Yen-Hsiang Chen:
Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation.
ISCAS (3) 2005: 2219-2222 |
| 1 | EE | Jin-Tai Yan,
Yen-Hsiang Chen,
Chia-Fang Lee:
Timing-Constrained Flexibility-Driven Routing Tree Construction.
IEICE Transactions 88-D(7): 1360-1368 (2005) |
