| 2009 |
|---|
| 35 | EE | Jin-Tai Yan,
Zhi-Wei Chen:
RDL pre-assignment routing for flip-chip designs.
ACM Great Lakes Symposium on VLSI 2009: 401-404 |
| 34 | EE | Jin-Tai Yan,
Zhi-Wei Chen:
Redundant wire insertion for yield improvement.
ACM Great Lakes Symposium on VLSI 2009: 409-412 |
| 2008 |
|---|
| 33 | EE | Jin-Tai Yan:
Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction.
ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
| 2007 |
|---|
| 32 | EE | Jin-Tai Yan,
Zhi-Wei Chen,
Ming-Yuen Wu:
Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity.
ISCAS 2007: 3395-3398 |
| 31 | EE | Jin-Tai Yan,
Bo-Yi Chiang:
Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization.
VLSI Design 2007: 899-906 |
| 2006 |
|---|
| 30 | EE | Jin-Tai Yan,
Bo-Yi Chiang,
Shi-Qin Huang:
Width and Timing-Constrained Wire Sizing for Critical Area Minimization.
APCCAS 2006: 1276-1279 |
| 29 | EE | Jin-Tai Yan,
Zhi-Wei Chen,
Chia-Wei Wu,
Ming-Yuen Wu:
Optimal Network Analysis in Hierarchical Power Quad-Grids.
APCCAS 2006: 1289-1292 |
| 28 | EE | Jin-Tai Yan,
Kai-Ping Lin,
Yue-Fong Luo:
Floorplan-aware decoupling capacitance budgeting on equivalent circuit model.
ISCAS 2006 |
| 27 | EE | Jin-Tai Yan,
Yen-Hsiang Chen,
Chia-Fang Lee,
Ming-Ching Huang:
Multilevel timing-constrained full-chip routing in hierarchical quad-grid model.
ISCAS 2006 |
| 26 | EE | Jin-Tai Yan,
Kuen-Ming Lin,
Yen-Hsiang Chen:
Optimal shielding insertion for inductive noise avoidance.
ISCAS 2006 |
| 25 | EE | Jin-Tai Yan,
Bo-Yi Chiang,
Chia-Fang Lee:
Timing-constrained yield-driven wire sizing for critical area minimization.
ISCAS 2006 |
| 24 | EE | Jin-Tai Yan,
Chia-Fang Lee,
Yen-Hsiang Chen:
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing.
VLSI Design 2006: 147-152 |
| 2005 |
|---|
| 23 | EE | Jin-Tai Yan,
Yen-Hsiang Chen,
Chia-Wei Wu:
Probabilistic congestion prediction in hierarchical quad-grid model.
ISCAS (2) 2005: 1350-1353 |
| 22 | EE | Jin-Tai Yan,
Chia-Wei Wu,
Yen-Hsiang Chen:
Wiring area optimization in floorplan-aware hierarchical power grids.
ISCAS (2) 2005: 1366-1369 |
| 21 | EE | Jin-Tai Yan,
Tzu-Ya Wang,
Yu-Cheng Lee:
Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points.
ISCAS (2) 2005: 1370-1373 |
| 20 | EE | Jin-Tai Yan,
Kai-Ping Lin,
Yen-Hsiang Chen:
Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation.
ISCAS (3) 2005: 2219-2222 |
| 19 | EE | Jin-Tai Yan,
Yen-Hsiang Chen,
Chia-Fang Lee:
Timing-Constrained Flexibility-Driven Routing Tree Construction.
IEICE Transactions 88-D(7): 1360-1368 (2005) |
| 2004 |
|---|
| 18 | EE | Jin-Tai Yan,
Shun-Hua Lin:
Timing-constrained congestion-driven global routing.
ASP-DAC 2004: 683-686 |
| 2002 |
|---|
| 17 | EE | Shuenn-Shi Chen,
Wang-Dauh Tseng,
Jin-Tai Yan,
Sao-Jie Chen:
Printed circuit board routing and package layout codesign.
APCCAS (1) 2002: 155-158 |
| 2000 |
|---|
| 16 | EE | Jin-Tai Yan:
Three-layer bubble-sorting-based nonManhattan channel routing.
ACM Trans. Design Autom. Electr. Syst. 5(3): 726-734 (2000) |
| 1999 |
|---|
| 15 | EE | Jin-Tai Yan:
An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1519-1526 (1999) |
| 14 | EE | Jin-Tai Yan:
An improved optimal algorithm for bubble-sorting-basednon-Manhattan channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 163-171 (1999) |
| 1998 |
|---|
| 13 | EE | Jin-Tai Yan:
Routing Space Estimation and Assignment for Macro-Cell Placement.
Journal of Circuits, Systems, and Computers 8(4): 435-446 (1998) |
| 1996 |
|---|
| 12 | EE | Jin-Tai Yan:
An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell Placement.
Great Lakes Symposium on VLSI 1996: 100- |
| 11 | EE | Jin-Tai Yan:
A simple yet effective genetic approach for the orientation assignment on cell-based layout.
VLSI Design 1996: 33-36 |
| 10 | EE | Jin-Tai Yan,
Pei-Yung Hsiao:
Minimizing the number of switchboxes for region definition and ordering assignment.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(3): 336-347 (1996) |
| 1995 |
|---|
| 9 | EE | Jin-Tai Yan:
Region definition and ordering assignment with the minimization of the number of switchboxes.
ASP-DAC 1995 |
| 8 | EE | Jin-Tai Yan:
An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement.
Great Lakes Symposium on VLSI 1995: 128-131 |
| 7 | EE | Jin-Tai Yan:
Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning.
ICCD 1995: 236- |
| 6 | EE | Jin-Tai Yan:
An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering.
ICCD 1995: 366-371 |
| 5 | EE | Jin-Tai Yan,
Pei-Yung Hsiao:
A new fuzzy-clustering-based approach for two-way circuit partitioning.
VLSI Design 1995: 359-364 |
| 1994 |
|---|
| 4 | | Jin-Tai Yan,
Pei-Yung Hsiao:
Region Definition of Minimizing the Number of Switchboxes and Ordering Assignment.
ISCAS 1994: 105-108 |
| 3 | | Paul-Waie Shew,
Jin-Tai Yan,
Pei-Yung Hsiao,
Yong-Ching Lim:
Efficient Algorithms for Two and Three-Layer Over-the-Cell Channel Routing.
ISCAS 1994: 183-186 |
| 2 | | Jin-Tai Yan,
Pei-Yung Hsiao:
A Fuzzy Clustering Algorithm for Graph Bisection.
Inf. Process. Lett. 52(5): 259-263 (1994) |
| 1993 |
|---|
| 1 | EE | Lih-Der Chang,
Pei-Yung Hsiao,
Jin-Tai Yan,
Paul-Waie Shew:
A robust over-the-cell channel router.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1592-1599 (1993) |
