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Maryam Ashouei

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2008
8EEMaryam Ashouei, Adit D. Singh, Abhijit Chatterjee: Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS. VLSI Design 2008: 27-32
2007
7EEMuhammad Mudassar Nisar, Maryam Ashouei, Abhijit Chatterjee: Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums. IOLTS 2007: 173-182
6EEMaryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril: Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. VLSI Design 2007: 711-716
5EEMaryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee: Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors. VTS 2007: 125-130
2006
4EEMaryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee: Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study. European Test Symposium 2006: 35-42
3EEMaryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak: Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. VLSI Design 2006: 606-612
2EEMaryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee: Design of Soft Error Resilient Linear Digital Filters Using Checksum-Based Probabilistic Error Correction. VTS 2006: 208-213
2005
1EEMaryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De: A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. ICCD 2005: 567-573

Coauthor Index

1Soumendu Bhattacharya [2] [4] [5]
2Abhijit Chatterjee [1] [2] [3] [4] [5] [6] [7] [8]
3Vivek De [1] [3]
4Abdulkadir Utku Diril [6]
5T. M. Mak [3]
6Muhammad Mudassar Nisar [6] [7]
7Adit D. Singh [1] [3] [6] [8]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)