| |
| 2006 | ||
|---|---|---|
| 4 | EE | Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang: Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. ISCAS 2006 |
| 3 | EE | Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee: Timing-constrained yield-driven wire sizing for critical area minimization. ISCAS 2006 |
| 2 | EE | Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen: Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. VLSI Design 2006: 147-152 |
| 2005 | ||
| 1 | EE | Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee: Timing-Constrained Flexibility-Driven Routing Tree Construction. IEICE Transactions 88-D(7): 1360-1368 (2005) |
| 1 | Yen-Hsiang Chen | [1] [2] [4] |
| 2 | Bo-Yi Chiang | [3] |
| 3 | Ming-Ching Huang | [4] |
| 4 | Jin-Tai Yan | [1] [2] [3] [4] |