![]() | ![]() |
2006 | ||
---|---|---|
1 | EE | K. A. Rajagopal, R. Sivakumar, N. V. Arvind, C. Sreeram, Vish Visvanathan, Shailendra Dhuri, Roopesh Chander, Patrick Fortner, Subra Sripada, Qiuyang Wu: A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff. VLSI Design 2006: 277-282 |
1 | N. V. Arvind | [1] |
2 | Roopesh Chander | [1] |
3 | Shailendra Dhuri | [1] |
4 | Patrick Fortner | [1] |
5 | K. A. Rajagopal | [1] |
6 | R. Sivakumar | [1] |
7 | C. Sreeram | [1] |
8 | Subra Sripada | [1] |
9 | Qiuyang Wu | [1] |