ISQED 2008:
San Jose,
California,
USA
9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA.
IEEE Computer Society 2008, ISBN 978-0-7695-3117-5 BibTeX
Tutorials
Plenary Session
Power Conscious Memories
- Mark Lysinger, François Jacquet, Mehdi Zamanian, David McClure, Philippe Roche, Naren Sahoo, John Russell:
A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS.
23-29
Electronic Edition (link) BibTeX
- Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar:
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation.
30-34
Electronic Edition (link) BibTeX
- Maurizio Skerlj, Paolo Ienne:
Error Protected Data Bus Inversion Using Standard DRAM Components.
35-42
Electronic Edition (link) BibTeX
- Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas:
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.
43-46
Electronic Edition (link) BibTeX
Speed-Up and Timing of Integrated Circuits
- Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis:
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.
47-52
Electronic Edition (link) BibTeX
- Vineeth Veetil, Dennis Sylvester, David Blaauw:
Fast and Accurate Waveform Analysis with Current Source Models.
53-56
Electronic Edition (link) BibTeX
- Xin Wang, Alireza Kasnavi, Harold Levy:
An Efficient Method for Fast Delay and SI Calculation Using Current Source Models.
57-61
Electronic Edition (link) BibTeX
- Yi Wang, Xuan Zeng, Jun Tao, Hengliang Zhu, Xu Luo, Changhao Yan, Wei Cai:
Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model.
62-67
Electronic Edition (link) BibTeX
SER and Noise Tolerance
- Avijit Dutta, Abhijit Jas:
Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes.
68-73
Electronic Edition (link) BibTeX
- Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang:
Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths.
74-77
Electronic Edition (link) BibTeX
- Jiun-Kuan Wu, Tsung-Yi Wu, Liang-Ying Lu, Kuang-Yao Chen:
IR Drop Reduction via a Flip-Flop Resynthesis Technique.
78-83
Electronic Edition (link) BibTeX
- Daniel A. Andersson, Simon Kristiansson, Lars J. Svensson, Per Larsson-Edefors, Kjell O. Jeppson:
Noise Interaction Between Power Distribution Grids and Substrate.
84-89
Electronic Edition (link) BibTeX
Luncheon Keynote Speech
Robust SRAM and Analog Circuits
- Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran:
Fundamental Data Retention Limits in SRAM Standby Experimental Results.
92-97
Electronic Edition (link) BibTeX
- Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Quality of a Bit (QoB): A New Concept in Dependable SRAM.
98-102
Electronic Edition (link) BibTeX
- Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham:
Cache Design for Low Power and High Yield.
103-107
Electronic Edition (link) BibTeX
- Xin Li, Yu Cao:
Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations.
108-113
Electronic Edition (link) BibTeX
- Tian Xia, Stephen Wyatt:
High Output Resistance and Wide Swing Voltage Charge Pump Circuit.
114-117
Electronic Edition (link) BibTeX
Power and Thermal Management
- Krishnan Sundaresan, Nihar R. Mahapatra:
Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses.
118-122
Electronic Edition (link) BibTeX
- Saravanan Ramamoorthy, Haibo Wang, Sarma B. K. Vrudhula:
A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design.
123-126
Electronic Edition (link) BibTeX
- Joseph F. Ryan, Benton H. Calhoun:
Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation.
127-132
Electronic Edition (link) BibTeX
- Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai:
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM.
133-136
Electronic Edition (link) BibTeX
- Shervin Sharifi, Chunchen Liu, Tajana Simunic Rosing:
Accurate Temperature Estimation for Efficient Thermal Management.
137-142
Electronic Edition (link) BibTeX
Process Variations
System and Circuit Synthesis
Process,
Characterization,
and Temperature-Aware Design
- Yu Zhong, Martin D. F. Wong:
Thermal-Aware IR Drop Analysis in Large Power Grid.
194-199
Electronic Edition (link) BibTeX
- Amit Goel, Sarma B. K. Vrudhula, Feroze Taraporevala, Praveen Ghanta:
A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations.
200-206
Electronic Edition (link) BibTeX
- Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev:
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model.
207-212
Electronic Edition (link) BibTeX
- Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda:
Characterization of Standard Cells for Intra-Cell Mismatch Variations.
213-219
Electronic Edition (link) BibTeX
- Tao Li, Zhiping Yu:
Full-Chip Leakage Verification for Manufacturing Considering Process Variations.
220-223
Electronic Edition (link) BibTeX
Processor Test Verification / Delay Diagnosis
- Sangeetha Sudhakrishnan, Liying Su, Jose Renau:
Processor Verification with hwBugHunt.
224-229
Electronic Edition (link) BibTeX
- Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi:
Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions.
230-235
Electronic Edition (link) BibTeX
- Jian Kang, Sharad C. Seth, Yi-Shing Chang, Vijay Gangaram:
Efficient Selection of Observation Points for Functional Tests.
236-241
Electronic Edition (link) BibTeX
- Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas:
A Novel Test Generation Methodology for Adaptive Diagnosis.
242-245
Electronic Edition (link) BibTeX
- Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski:
Timing-Aware Multiple-Delay-Fault Diagnosis.
246-253
Electronic Edition (link) BibTeX
Embedded Technical Sessions
- Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos:
A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs.
257-260
Electronic Edition (link) BibTeX
- Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates.
261-266
Electronic Edition (link) BibTeX
- Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen:
A Statistic-Based Approach to Testability Analysis.
267-270
Electronic Edition (link) BibTeX
- Feng Liu, Jin He, Yue Fu, Jinhua Hu, Wei Bian, Yan Song, Xing Zhang, Mansun Chan:
Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes.
271-276
Electronic Edition (link) BibTeX
- Tsu-Shuan Chang, Manish Kumar, Teng-Sheng Moh, Chung-Li Tseng:
On the Feasibility of Obtaining a Globally Optimal Floorplanning for an L-shaped Layout Problem.
277-282
Electronic Edition (link) BibTeX
- John Ferguson, Robert Todd:
Architecting for Physical Verification Performance and Scaling.
283-288
Electronic Edition (link) BibTeX
- Haixia Yan, Qiang Zhou, Xianlong Hong:
Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm.
289-292
Electronic Edition (link) BibTeX
- Neehar Jandhyala, Lili He, Morris Jones:
CMOS Based Low Cost Temperature Sensor.
293-296
Electronic Edition (link) BibTeX
- Sukumar Jairam, S. M. Stalin, Jean-Yves Oberle, H. Udayakumar:
An SSO Based Methodology for EM Emission Estimation from SoCs.
297-300
Electronic Edition (link) BibTeX
- Muzhou Shao:
Fast Timing Update under the Effect of IR Drop.
301-304
Electronic Edition (link) BibTeX
- Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun:
Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations.
305-310
Electronic Edition (link) BibTeX
- Sherif A. Tawfik, Volkan Kursun:
Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations.
311-316
Electronic Edition (link) BibTeX
- Ricky Yiu-kee Choi, Chi-Ying Tsui:
A Low Energy Two-Step Successive Approximation Algorithm for ADC Design.
317-320
Electronic Edition (link) BibTeX
- Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto:
Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration.
321-324
Electronic Edition (link) BibTeX
- Srinivasa R. S. T. G, Jandhyala Srivatsava, Narahari Tondamuthuru R:
Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies.
325-329
Electronic Edition (link) BibTeX
- Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos:
Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design.
330-333
Electronic Edition (link) BibTeX
- C. R. Venugopal, Prasanth Soraiyur, Jagannath Rao:
Evaluation of the PTSI Crosstalk Noise Analysis Tool and Development of an Automated Spice Correlation Suite to Enable Accuracy Validation.
334-337
Electronic Edition (link) BibTeX
- Qing Su, Charles Chiang, Jamil Kawa:
Hotspot Based Yield Prediction with Consideration of Correlations.
338-343
Electronic Edition (link) BibTeX
- Maharaj Mukherjee, Kanad Chakraborty:
A Randomized Greedy Algorithm for the Pattern Fill Problem for DFM Applications.
344-347
Electronic Edition (link) BibTeX
- José Carlos S. Palma, César A. M. Marcon, Fabiano Hessel, Eduardo Bezerra, Guilherme Rohde, Luciano Azevedo, Carlos Eduardo Reif, Carolina Metzler:
A Passive 915 MHz UHF RFID Tag.
348-351
Electronic Edition (link) BibTeX
- Jae-Seok Yang, Andrew R. Neureuther:
Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner.
352-356
Electronic Edition (link) BibTeX
- Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong:
DFM Based Detailed Routing Algorithm for ECP and CMP.
357-360
Electronic Edition (link) BibTeX
- Toshinori Sato, Shingo Watanabe:
Instruction Scheduling for Variation-Originated Variable Latencies.
361-364
Electronic Edition (link) BibTeX
- Norma Rodriguez, Li Song, Shishir Shroff, Kuang Han Chen, Taber Smith, Wilbur Luo:
Hotspot Prevention Using CMP Model in Design Implementation Flow.
365-368
Electronic Edition (link) BibTeX
- Young-Gu Kim, Soo-Hwan Kim, Hoon Lim, Sanghoon Lee, Keun-Ho Lee, Young-Kwan Park, Moon-Hyun Yoo:
The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era.
369-372
Electronic Edition (link) BibTeX
- Ratnakar Goyal, Harindranath Parameswaran, Sachin Shrivastava:
Computation of Waveform Sensitivity Using Geometric Transforms for SSTA.
373-378
Electronic Edition (link) BibTeX
- Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy:
On Efficient and Robust Constraint Generation for Practical Layout Legalization.
379-384
Electronic Edition (link) BibTeX
- Charbel J. Akl, Magdy A. Bayoumi:
Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family.
385-390
Electronic Edition (link) BibTeX
- Eric Karl, Dennis Sylvester, David Blaauw:
Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures.
391-395
Electronic Edition (link) BibTeX
- Parastoo Nikaeen, Boris Murmann, Robert W. Dutton:
Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs.
396-400
Electronic Edition (link) BibTeX
- Vinay Jain, Payman Zarkesh-Ha:
Analytical Noise-Rejection Model Based on Short Channel MOSFET.
401-406
Electronic Edition (link) BibTeX
- Michael N. Skoufis, Kedar Karmarkar, Themistoklis Haniotakis, Spyros Tragoudas:
A High-Performance Bus Architecture for Strongly Coupled Interconnects.
407-410
Electronic Edition (link) BibTeX
- Zahra Sadat Ebadi, Resve A. Saleh:
A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS.
411-416
Electronic Edition (link) BibTeX
- Alicia Strang, David Potts, Shankar Hemmady:
A Holistic Approach to SoC Verification.
417-422
Electronic Edition (link) BibTeX
- Nathaniel August:
A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel’s Test Chips.
423-428
Electronic Edition (link) BibTeX
- Jae Wook Kim, Boris Murmann, Robert W. Dutton:
Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium Devices.
429-432
Electronic Edition (link) BibTeX
- Anil Deshpande:
Verification of IP-Core Based SoC's.
433-436
Electronic Edition (link) BibTeX
- Matthew G. Stout, Kenneth P. Tumin:
Innovative Test Solutions for Pin-Limited Microcontrollers.
437-440
Electronic Edition (link) BibTeX
- Ganesh R. Shamnur, Rajesh R. Berigei:
XStatic: A Simulation Based ESD Verification and Debug Environment.
441-444
Electronic Edition (link) BibTeX
- Sachin Shrivastava, Harindranath Parameswaran:
Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping.
445-449
Electronic Edition (link) BibTeX
- Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy:
Cell Swapping Based Migration Methodology for Analog and Custom Layouts.
450-455
Electronic Edition (link) BibTeX
- Paul Pao-Fang Cheng:
A Knowledge-Based Tool for Generating and Verifying Hardware-Ready Embedded Memory Models.
456-459
Electronic Edition (link) BibTeX
- Ravi Surepeddi:
System Verilog for Quality of Results (QoR).
460-464
Electronic Edition (link) BibTeX
- Zhen Mu:
Power Delivery System: Sufficiency, Efficiency, and Stability.
465-469
Electronic Edition (link) BibTeX
- Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir:
Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability.
470-475
Electronic Edition (link) BibTeX
- Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, Chung-Kuan Cheng:
Clock Skew Analysis via Vector Fitting in Frequency Domain.
476-479
Electronic Edition (link) BibTeX
- Sridhar Joshi, Ravi Perumal, Kamesh V. Gadepally, Mark Young:
An Approach for a Comprehensive QA Methodology for the PDKs.
480-483
Electronic Edition (link) BibTeX
- Kamesh V. Gadepally, Mark Young, James Lin, Andy Franklin, Ravi Perumal, Sridhar Joshi:
Strategies for Quality CAD PDKs.
484-487
Electronic Edition (link) BibTeX
- Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang:
Variability Analysis for sub-100nm PD/SOI Sense-Amplifier.
488-491
Electronic Edition (link) BibTeX
- Manuel Sellier, Jean Michel Portal, Bertrand Borot, Steve Colquhoun, Richard Ferrant, Frédéric Boeuf, Alexis Farcy:
Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework.
492-497
Electronic Edition (link) BibTeX
- Rasit Onur Topaloglu:
Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics.
498-501
Electronic Edition (link) BibTeX
- Saurabh Sinha, Asha Balijepalli, Yu Cao:
A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design.
502-507
Electronic Edition (link) BibTeX
- Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler:
Adaptive Branch and Bound Using SAT to Estimate False Crosstalk.
508-513
Electronic Edition (link) BibTeX
- Peng-Yang Hung, Ying-Shu Lou, Yih-Lang Li:
Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing.
514-519
Electronic Edition (link) BibTeX
- Shinya Abe, Masanori Hashimoto, Takao Onoye:
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution.
520-525
Electronic Edition (link) BibTeX
- Sandeep Gupta, Jaya Singh, Abhijit Roy:
A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs.
526-530
Electronic Edition (link) BibTeX
- Yue Fu, Jin He, Feng Liu, Jie Feng, Chenyue Ma, Lining Zhang:
Study on the Si-Ge Nanowire MOSFETs with the Core-Shell Structure.
531-536
Electronic Edition (link) BibTeX
- Rupak Samanta, Ganesh Venkataraman, Nimay Shah, Jiang Hu:
Elastic Timing Scheme for Energy-Efficient and Robust Performance.
537-542
Electronic Edition (link) BibTeX
- Ning Lu:
Statistical Models and Frequency-Dependent Corner Models for Passive Devices.
543-548
Electronic Edition (link) BibTeX
- Enric Musoll:
A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors.
549-552
Electronic Edition (link) BibTeX
- DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De:
Analytical Model for the Propagation Delay of Through Silicon Vias.
553-556
Electronic Edition (link) BibTeX
- Salam D. Marougi:
Sampling Error Estimation in High-Speed Sampling Systems Introduced by the Presence of Phase Noise in the Sampling Clock.
557-563
Electronic Edition (link) BibTeX
- David Matschulat, César A. M. Marcon, Fabiano Hessel:
A QoS Scheduler for Real-Time Embedded Systems.
564-567
Electronic Edition (link) BibTeX
- James Helton, Chien-In Henry Chen, David M. Lin, James B. Y. Tsui:
FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver.
568-571
Electronic Edition (link) BibTeX
- Jeff Mueller, Resve A. Saleh:
A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks.
572-577
Electronic Edition (link) BibTeX
Plenary Session
Co-Design Applications for IC Packages
Tools and Interconnects
Sequential Analysis,
Defect Modeling,
and At-Speed Testing
Modeling and Analysis in Physical Design
- Dinesh Ganesan, Alexander V. Mitev, Janet Meiling Wang, Yu Cao:
Finite-Point Gate Model for Fast Timing and Power Analysis.
657-662
Electronic Edition (link) BibTeX
- Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors:
Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach.
663-669
Electronic Edition (link) BibTeX
- Hai Lan, Ralf Schmitt, Chuck Yuan:
Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces.
670-675
Electronic Edition (link) BibTeX
- Anand Rajaram, Raguram Damodaran, Arjun Rajagopal:
Practical Clock Tree Robustness Signoff Metrics.
676-679
Electronic Edition (link) BibTeX
- Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, K. Unlu:
Hierarchical Soft Error Estimation Tool (HSEET).
680-683
Electronic Edition (link) BibTeX
Emerging Technologies and Novel Applications
- Yiran Chen, Xiaobin Wang, Hai Li, Harry Liu, Dimitar V. Dimitrov:
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM).
684-690
Electronic Edition (link) BibTeX
- Arthur Nieuwoudt, Yehia Massoud:
Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect.
691-696
Electronic Edition (link) BibTeX
- Rajat Subhra Chakraborty, Swarup Bhunia:
Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar.
697-701
Electronic Edition (link) BibTeX
- Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif:
Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.
702-707
Electronic Edition (link) BibTeX
- Daniela De Venuto, Bruno Riccò:
High Resolution Read-Out Circuit for DNA Label-Free Detection System.
708-711
Electronic Edition (link) BibTeX
Statistical Timing
- Lin Xie, Azadeh Davoodi:
Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation.
712-717
Electronic Edition (link) BibTeX
- Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng:
Characterizing Intra-Die Spatial Correlation Using Spectral Density Method.
718-723
Electronic Edition (link) BibTeX
- Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud:
Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and Noise.
724-729
Electronic Edition (link) BibTeX
- Jui-Hsiang Liu, Jun-Kuei Zeng, Ai-Syuan Hong, Lumdo Chen, Charlie Chung-Ping Chen:
Process-Variation Statistical Modeling for VLSI Timing Analysis.
730-733
Electronic Edition (link) BibTeX
- Victoria Wang, Kanak Agarwal, Sani R. Nassif, Kevin J. Nowka, Dejan Markovic:
A Design Model for Random Process Variability.
734-737
Electronic Edition (link) BibTeX
Modern Processor Design
Modeling and Design of Reliable Circuits
Design for Manufacturing
- Kwangok Jeong, Andrew B. Kahng, Kambiz Samadi:
Quantified Impacts of Guardband Reduction on Design Process Outcomes.
790-797
Electronic Edition (link) BibTeX
- Uthman Alsaiari, Resve A. Saleh:
Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits.
798-803
Electronic Edition (link) BibTeX
- Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif:
A Root-Finding Method for Assessing SRAM Stability.
804-809
Electronic Edition (link) BibTeX
- Hailong Jiao, Lan Chen:
Cellwise OPC Based on Reduced Standard Cell Library.
810-814
Electronic Edition (link) BibTeX
- Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown:
On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits.
815-820
Electronic Edition (link) BibTeX
Structural Test
Advanced Design Methodologies
- Udo Sobe, Karl-Heinz Rooch, Andreas Ripp, Michael Pronath:
Robust Analog Design for Automotive Applications by Design Centering with Safe Operating Areas.
848-854
Electronic Edition (link) BibTeX
- Sherif A. Tawfik, Volkan Kursun:
Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation.
855-860
Electronic Edition (link) BibTeX
- Yu Zhou, Somnath Paul, Swarup Bhunia:
Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect.
861-866
Electronic Edition (link) BibTeX
- Zuying Luo, Sheldon X.-D. Tan:
Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method.
867-872
Electronic Edition (link) BibTeX
- Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong:
IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization.
873-876
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:26:15 2009
by Michael Ley (ley@uni-trier.de)
