Tiago Muller Gil Cardoso

2008
2	EE	Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis: Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. ISQED 2008: 47-52
2006
1	EE	Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis: Fast disjoint transistor networks from BDDs. SBCCI 2006: 137-142

Coauthor Index

1	Felipe S. Marques	[1]
2	Felipe de Souza Marques	[2]
3	André Inácio Reis	[1] [2]
4	Renato P. Ribas	[1] [2]
5	Leomar S. da Rosa Jr.	[1] [2]
6	Sachin S. Sapatnekar	[1]