Payman Zarkesh-Ha

2009
16	EE	Rani S. Ghaida, Payman Zarkesh-Ha: A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects. J. Electronic Testing 25(1): 67-77 (2009)
2008
15	EE	Vinay Jain, Payman Zarkesh-Ha: Analytical Noise-Rejection Model Based on Short Channel MOSFET. ISQED 2008: 401-406
2007
14	EE	Rani S. Ghaida, Payman Zarkesh-Ha: Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model. DFT 2007: 59-67
13	EE	Payman Zarkesh-Ha, Ken Doniger: Stochastic interconnect layout sensitivity model. SLIP 2007: 9-14
2004
12	EE	Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Bendix: Prediction of interconnect adjacency distribution: derivation, validation, and applications. SLIP 2004: 99-106
11		James W. Joyner, Payman Zarkesh-Ha, James D. Meindl: Global interconnect design in a three-dimensional system-on-a-chip. IEEE Trans. VLSI Syst. 12(4): 367-372 (2004)
2003
10		Dennis Sylvester, Dirk Stroobandt, Louis Scheffer, Payman Zarkesh-Ha: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings ACM 2003
9	EE	Payman Zarkesh-Ha, Ken Doniger, William Loh, Dechang Sun, Rick Stephani, Gordon Priebe: A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors. ICCD 2003: 84-89
8	EE	Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger, William Loh, Peter Wright: Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow. ISQED 2003: 405-409
7	EE	Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Wright: Prediction of interconnect pattern density distribution: derivation, validation, and applications. SLIP 2003: 85-91
2002
6	EE	James D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl: Interconnect opportunities for gigascale integration. IBM Journal of Research and Development 46(2-3): 245-264 (2002)
2001
5	EE	James W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl: Impact of three-dimensional architectures on interconnects in gigascale integration. IEEE Trans. VLSI Syst. 9(6): 922-928 (2001)
2000
4	EE	Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl: Prediction of interconnect fan-out distribution using Rent's rule. SLIP 2000: 107-112
3	EE	James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl: Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. SLIP 2000: 123-127
2	EE	Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl: Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. IEEE Trans. VLSI Syst. 8(6): 649-659 (2000)
1	EE	Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl: A compact physical via blockage model. IEEE Trans. VLSI Syst. 8(6): 689-692 (2000)

Coauthor Index

1	Peter Bendix	[12]
2	Qiang Chen	[1]
3	Jeffrey A. Davis	[1] [2] [3] [4] [5] [6]
4	Ken Doniger	[7] [8] [9] [12] [13]
5	Rani S. Ghaida	[14] [16]
6	Vinay Jain	[15]
7	James W. Joyner	[3] [5] [11]
8	Paul A. Kohl	[6]
9	S. Lakshminarayann	[8]
10	William Loh	[4] [7] [8] [9] [12]
11	Kevin P. Martin	[6]
12	James D. Meindl	[1] [2] [3] [4] [5] [6] [11]
13	Chirag S. Patel	[6]
14	Gordon Priebe	[9]
15	Louis Scheffer	[10]
16	Rick Stephani	[9]
17	Dirk Stroobandt	[10]
18	Dechang Sun	[9]
19	Dennis Sylvester	[10]
20	Raguraman Venkatesan	[5]
21	Peter Wright	[7] [8]

Colors in the list of coauthors