Enric Musoll

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9EEEnric Musoll: Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures. ISQED 2009: 201-207
8EEEnric Musoll: A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors. ISQED 2008: 549-552
7EEEnric Musoll: Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gating. SASP 2008: 89-94
6EEEnric Musoll: Speculating to reduce unnecessary power consumption. ACM Trans. Embedded Comput. Syst. 2(4): 509-536 (2003)
5EEEnric Musoll: Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors. MICRO 1999: 238-247
4EEEnric Musoll, Tomás Lang, Jordi Cortadella: Working-zone encoding for reducing the energy in microprocessor address buses. IEEE Trans. VLSI Syst. 6(4): 568-572 (1998)
3EEEnric Musoll, Tomás Lang, Jordi Cortadella: Exploiting the locality of memory references to reduce the address bus energy. ISLPED 1997: 202-207
2EEEnric Musoll, Jordi Cortadella: High-level synthesis techniques for reducing the activity of functional units. ISLPD 1995: 99-104
1EEEnric Musoll, Jordi Cortadella: Scheduling and resource binding for low power. ISSS 1995: 104-109

Coauthor Index

1Jordi Cortadella [1] [2] [3] [4]
2Tomás Lang [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)