| 2009 |
|---|
| 9 | EE | Enric Musoll:
Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures.
ISQED 2009: 201-207 |
| 2008 |
|---|
| 8 | EE | Enric Musoll:
A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors.
ISQED 2008: 549-552 |
| 7 | EE | Enric Musoll:
Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gating.
SASP 2008: 89-94 |
| 2003 |
|---|
| 6 | EE | Enric Musoll:
Speculating to reduce unnecessary power consumption.
ACM Trans. Embedded Comput. Syst. 2(4): 509-536 (2003) |
| 1999 |
|---|
| 5 | EE | Enric Musoll:
Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors.
MICRO 1999: 238-247 |
| 1998 |
|---|
| 4 | EE | Enric Musoll,
Tomás Lang,
Jordi Cortadella:
Working-zone encoding for reducing the energy in microprocessor address buses.
IEEE Trans. VLSI Syst. 6(4): 568-572 (1998) |
| 1997 |
|---|
| 3 | EE | Enric Musoll,
Tomás Lang,
Jordi Cortadella:
Exploiting the locality of memory references to reduce the address bus energy.
ISLPED 1997: 202-207 |
| 1995 |
|---|
| 2 | EE | Enric Musoll,
Jordi Cortadella:
High-level synthesis techniques for reducing the activity of functional units.
ISLPD 1995: 99-104 |
| 1 | EE | Enric Musoll,
Jordi Cortadella:
Scheduling and resource binding for low power.
ISSS 1995: 104-109 |
