| |
| 2009 | ||
|---|---|---|
| 6 | EE | Shingo Watanabe, Masanori Hashimoto, Toshinori Sato: A case for exploiting complex arithmetic circuits towards performance yield enhancement. ISQED 2009: 401-407 |
| 5 | EE | Toshinori Sato, Shingo Watanabe: Uncriticality-directed scheduling for tackling variation and power challenges. ISQED 2009: 820-825 |
| 2008 | ||
| 4 | EE | Toshinori Sato, Shingo Watanabe: Instruction Scheduling for Variation-Originated Variable Latencies. ISQED 2008: 361-364 |
| 3 | EE | Shingo Watanabe, Toshinori Sato: Uncriticality-Directed Low-Power Instruction Scheduling. ISVLSI 2008: 69-74 |
| 2 | EE | Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato: A Low-Power Instruction Issue Queue for Microprocessors. IEICE Transactions 91-C(4): 400-409 (2008) |
| 2007 | ||
| 1 | EE | Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato: Indirect Tag Search Mechanism for Instruction Window Energy Reduction. CIT 2007: 841-846 |
| 1 | Akihiro Chiyonobu | [1] [2] |
| 2 | Masanori Hashimoto | [6] |
| 3 | Toshinori Sato | [1] [2] [3] [4] [5] [6] |