Walter Anheier

2008
17	EE	Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler: Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. ISQED 2008: 508-513
16	EE	Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier: Crosstalk fault modeling in defective pair of interconnects. Integration 41(1): 27-37 (2008)
2007
15		Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier: XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects. DDECS 2007: 161-164
2006
14	EE	Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier: Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. DFT 2006: 336-344
13	EE	Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier: Reduction of Crosstalk Pessimism using Tendency Graph Approach. ICCD 2006
12	EE	Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier: Modeling of Crosstalk Fault in Defective Interconnects. PATMOS 2006: 340-349
2005
11	EE	Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel: A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. Asian Test Symposium 2005: 22-27
10	EE	Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel: ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. VLSI Design 2005: 354-359
2004
9	EE	Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel: Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. DFT 2004: 174-182
2000
8	EE	A. Schubert, Walter Anheier: On Random Pattern Testability of Cryptographic VLSI Cores. J. Electronic Testing 16(3): 185-192 (2000)
1999
7	EE	Frank Poehl, Walter Anheier: Quality Determination for Gate Delay Fault Tests Considering Three-State Elements. J. Electronic Testing 14(1-2): 49-55 (1999)
1998
6	EE	Ansgar Drolshagen, Walter Anheier, C. Chandra Sekhar: A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal. VLSI Design 1998: 122-127
1997
5	EE	Ansgar Drolshagen, H. Henkelmann, Walter Anheier: Processor Elements for the Standard Cell Implementation of Residue Number Systems. ASAP 1997: 116-123
1995
4	EE	Stefan Radtke, Jens Bargfrede, Walter Anheier: Distributed automatic test pattern generation with a parallel FAN algorithm. ICCD 1995: 698-
1994
3		Beom-Ik Cheon, Walter Anheier, Rainer Laur: A New Strategy for Test Pattern Generation in Sequential Circuits. ISCAS 1994: 77-80
2	EE	Bernd Lauterbach, Walter Anheier: Segmentation of Scanned Maps in Uniform Color Spaces. MVA 1994: 222-225
1993
1		B. Lauerbach, Walter Anheier: Segmentierung farbiger kartographischer Vorlagen in empfindungsgemäßen Farbräumen. DAGM-Symposium 1993: 733-740

Coauthor Index

1	Jens Bargfrede	[4] [13] [17]
2	Beom-Ik Cheon	[3]
3	Rolf Drechsler	[17]
4	Ansgar Drolshagen	[5] [6]
5	Kishore K. Duganapalli	[11] [12] [14] [15] [16]
6	Manfred Glesner	[13]
7	H. Henkelmann	[5]
8	Klaus Koch	[13] [17]
9	B. Lauerbach	[1]
10	Rainer Laur	[3]
11	Bernd Lauterbach	[2]
12	Volker Meyer	[9] [10]
13	Ajoy Kumar Palit	[9] [10] [11] [12] [14] [15] [16]
14	Murthy Palla	[13] [17]
15	Frank Poehl	[7]
16	Stefan Radtke	[4]
17	Jürgen Schlöffel	[9] [10] [11]
18	A. Schubert	[8]
19	C. Chandra Sekhar	[6]
20	Lei Wu	[11]

Colors in the list of coauthors