| 2008 |
|---|
| 6 | EE | Dinesh Ganesan,
Alexander V. Mitev,
Janet Meiling Wang,
Yu Cao:
Finite-Point Gate Model for Fast Timing and Power Analysis.
ISQED 2008: 657-662 |
| 2007 |
|---|
| 5 | EE | Alexander V. Mitev,
Michael Marefat,
Dongsheng Ma,
Janet Meiling Wang:
Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method.
ASP-DAC 2007: 468-473 |
| 4 | EE | Vineet Agarwal,
Jin Sun,
Alexander V. Mitev,
Janet Meiling Wang:
Delay Uncertainty Reduction by Interconnect and Gate Splitting.
ASP-DAC 2007: 690-695 |
| 3 | EE | Alexander V. Mitev,
Michael Marefat,
Dongsheng Ma,
Janet Meiling Wang:
Principle Hessian direction based parameter reduction with process variation.
ICCAD 2007: 632-637 |
| 2 | EE | Alexander V. Mitev,
Dinesh Ganesan,
Dheepan Shanmugasundaram,
Yu Cao,
Janet Meiling Wang:
A robust finite-point based gate model considering process variations.
ICCAD 2007: 692-697 |
| 1 | EE | Alexander V. Mitev,
Michael Marefat,
Dongsheng Ma,
Janet Meiling Wang:
Principle hessian direction based parameter reduction for interconnect networks with process variation.
SLIP 2007: 41-46 |
