| 2008 |
|---|
| 11 | EE | Yi Zhu,
Jianhua Liu,
Haikun Zhu,
Chung-Kuan Cheng:
Timing-power optimization for mixed-radix Ling adders by integer linear programming.
ASP-DAC 2008: 131-137 |
| 10 | EE | Ling Zhang,
Jianhua Liu,
Haikun Zhu,
Chung-Kuan Cheng,
Masanori Hashimoto:
High performance current-mode differential logic.
ASP-DAC 2008: 720-725 |
| 9 | EE | Ling Zhang,
Wenjian Yu,
Haikun Zhu,
Alina Deutsch,
George A. Katopis,
Daniel M. Dreps,
Ernest S. Kuh,
Chung-Kuan Cheng:
Low power passive equalizer optimization using tritonic step response.
DAC 2008: 570-573 |
| 8 | EE | Ling Zhang,
Wenjian Yu,
Haikun Zhu,
Wanping Zhang,
Chung-Kuan Cheng:
Clock Skew Analysis via Vector Fitting in Frequency Domain.
ISQED 2008: 476-479 |
| 2007 |
|---|
| 7 | EE | Jianhua Liu,
Yi Zhu,
Haikun Zhu,
Chung-Kuan Cheng,
John Lillis:
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space.
ASP-DAC 2007: 609-615 |
| 6 | EE | Haikun Zhu,
Yi Zhu,
Chung-Kuan Cheng,
David M. Harris:
An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization.
ASP-DAC 2007: 616-621 |
| 5 | EE | Haikun Zhu,
Rui Shi,
Chung-Kuan Cheng,
Hongyu Chen:
Approaching Speed-of-light Distortionless Communication for On-chip Interconnect.
ASP-DAC 2007: 684-689 |
| 4 | EE | Chun-Chen Liu,
Haikun Zhu,
Chung-Kuan Cheng:
Passive compensation for high performance inter-chip communication.
ICCD 2007: 547-552 |
| 2006 |
|---|
| 3 | EE | Haikun Zhu,
Chung-Kuan Cheng,
Ronald L. Graham:
On the construction of zero-deficiency parallel prefix circuits with minimum depth.
ACM Trans. Design Autom. Electr. Syst. 11(2): 387-409 (2006) |
| 2005 |
|---|
| 2 | EE | Haikun Zhu,
Chung-Kuan Cheng,
Ronald L. Graham:
Constructing zero-deficiency parallel prefix adder of minimum depth.
ASP-DAC 2005: 883-888 |
| 2003 |
|---|
| 1 | EE | Jianhua Liu,
Shuo Zhou,
Haikun Zhu,
Chung-Kuan Cheng:
An Algorithmic Approach for Generic Parallel Adders.
ICCAD 2003: 734-740 |
