Zuying Luo

2008
15	EE	Zuying Luo, Sheldon X.-D. Tan: Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method. ISQED 2008: 867-872
2006
14	EE	Zuying Luo: General transistor-level methodology on VLSI low-power design. ACM Great Lakes Symposium on VLSI 2006: 115-118
13	EE	Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu: Time-domain analysis methodology for large-scale RLC circuits and its applications. Science in China Series F: Information Sciences 49(5): 665-680 (2006)
2005
12	EE	Yongjun Xu, Jinghua Chen, Zuying Luo, Xiaowei Li: Vector extraction for average total power estimation. ASP-DAC 2005: 1086-1089
11	EE	Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: VLSI on-chip power/ground network optimization considering decap leakage currents. ASP-DAC 2005: 735-738
10	EE	Yici Cai, Jin Shi, Zuying Luo, Xianlong Hong: Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain. J. Comput. Sci. Technol. 20(2): 224-230 (2005)
2004
9	EE	Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. ASP-DAC 2004: 505-510
8		Yongjun Xu, Zuying Luo, Xiaowei Li: A maximum total leakage current estimation method. ISCAS (2) 2004: 757-760
7		Weikun Guo, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong: Partial random walk for large linear network analysis. ISCAS (5) 2004: 173-177
6	EE	Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong: Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling. ISQED 2004: 63-68
5	EE	Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. PATMOS 2004: 433-441
4	EE	Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai: Area minimization of power distribution network using efficient nonlinear programming techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1086-1094 (2004)
3	EE	Yongjun Xu, Zuying Luo, Xiaowei Li, Li-Jian Li, Xianlong Hong: Leakage Current Estimation of CMOS Circuit with Stack Effect. J. Comput. Sci. Technol. 19(5): 708-717 (2004)
2003
2	EE	Yongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li: Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits. Asian Test Symposium 2003: 196-201
2002
1	EE	Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min: Test Power Optimization Techniques for CMOS Circuits. Asian Test Symposium 2002: 332-337

Coauthor Index

1	Yici Cai	[4] [5] [6] [9] [10] [11] [13]
2	Jinghua Chen	[12]
3	Zhiguo Chen	[2]
4	Chung-Kuan Cheng	[4]
5	Wayne Wei-Ming Dai	[4]
6	Jingjing Fu	[5] [9] [11] [13]
7	Jun Gu	[4]
8	Weikun Guo	[7]
9	Xianlong Hong	[3] [4] [5] [6] [7] [9] [10] [11] [13]
10	Huawei Li	[1]
11	Li-Jian Li	[3]
12	Xiaowei Li	[1] [2] [3] [8] [12]
13	Yinghua Min	[1]
14	Zhu Pan	[5] [6] [9] [11] [13]
15	Jin Shi	[10]
16	Sheldon X.-D. Tan (Xiang-Dong Tan)	[5] [6] [7] [9] [11] [13] [15]
17	Xiaoyi Wang	[13]
18	Xiaohai Wu	[4]
19	Yongjun Xu	[2] [3] [8] [12]
20	Shiyuan Yang	[1]