2009 |
23 | EE | Michael Brown,
Cyrus Bazeghi,
Matthew R. Guthaus,
Jose Renau:
Measuring and modeling variabilityusing low-cost FPGAs.
FPGA 2009: 286 |
2008 |
22 | EE | Francisco J. Mesa-Martinez,
Michael Brown,
Joseph Nayfach-Battilana,
Jose Renau:
Measuring power and temperature from real processors.
IPDPS 2008: 1-5 |
21 | EE | Sangeetha Sudhakrishnan,
Liying Su,
Jose Renau:
Processor Verification with hwBugHunt.
ISQED 2008: 224-229 |
20 | EE | Sangeetha Sudakrishnan,
Janaki T. Madhavan,
E. James Whitehead Jr.,
Jose Renau:
Understanding bug fix patterns in verilog.
MSR 2008: 39-42 |
2007 |
19 | EE | Francisco J. Mesa-Martinez,
Michael Brown,
Joseph Nayfach-Battilana,
Jose Renau:
Measuring performance, power, and temperature from real processors.
Experimental Computer Science 2007: 16 |
18 | EE | Francisco J. Mesa-Martinez,
Joseph Nayfach-Battilana,
Jose Renau:
Power model validation through thermal measurements.
ISCA 2007: 302-311 |
17 | EE | Francisco J. Mesa-Martinez,
Jose Renau:
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning.
MICRO 2007: 236-248 |
16 | EE | Cyrus Bazeghi,
Francisco J. Mesa-Martinez,
Brian Greskamp,
Josep Torrellas,
Jose Renau:
Estimating design time for system circuits.
VLSI-SoC 2007: 60-65 |
2006 |
15 | EE | Francisco J. Mesa-Martinez,
Michael C. Huang,
Jose Renau:
SEED: scalable, efficient enforcement of dependences.
PACT 2006: 254-264 |
14 | EE | Wei Liu,
James Tuck,
Luis Ceze,
Wonsun Ahn,
Karin Strauss,
Jose Renau,
Josep Torrellas:
POSH: a TLS compiler that exploits program structure.
PPOPP 2006: 158-167 |
13 | EE | Jose Renau,
Karin Strauss,
Luis Ceze,
Wei Liu,
Smruti R. Sarangi,
James Tuck,
Josep Torrellas:
Energy-Efficient Thread-Level Speculation.
IEEE Micro 26(1): 80-91 (2006) |
12 | EE | Luis Ceze,
Karin Strauss,
James Tuck,
Josep Torrellas,
Jose Renau:
CAVA: Using checkpoint-assisted value prediction to hide L2 misses.
TACO 3(2): 182-208 (2006) |
2005 |
11 | EE | Jose Renau,
James Tuck,
Wei Liu,
Luis Ceze,
Karin Strauss,
Josep Torrellas:
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation.
ICS 2005: 179-188 |
10 | EE | Jose Renau,
Karin Strauss,
Luis Ceze,
Wei Liu,
Smruti R. Sarangi,
James Tuck,
Josep Torrellas:
Thread-Level Speculation on a CMP can be energy efficient.
ICS 2005: 219-228 |
9 | EE | Cyrus Bazeghi,
Francisco J. Mesa-Martinez,
Jose Renau:
uComplexity: Estimating Processor Design Effort.
MICRO 2005: 209-218 |
2003 |
8 | EE | Michael C. Huang,
Jose Renau,
Josep Torrellas:
Positional Adaptation of Processors: Application to Energy Reduction.
ISCA 2003: 157-168 |
7 | EE | Basilio B. Fraguela,
Jose Renau,
Paul Feautrier,
David A. Padua,
Josep Torrellas:
Programming the FlexRAM parallel intelligent memory system.
PPOPP 2003: 49-60 |
2002 |
6 | EE | Michael C. Huang,
Jose Renau,
Josep Torrellas:
Energy-efficient hybrid wakeup logic.
ISLPED 2002: 196-201 |
5 | EE | José F. Martínez,
Jose Renau,
Michael C. Huang,
Milos Prvulovic,
Josep Torrellas:
Cherry: checkpointed early resource recycling in out-of-order microprocessors.
MICRO 2002: 3-14 |
2001 |
4 | EE | Michael C. Huang,
Jose Renau,
Seung-Moon Yoo,
Josep Torrellas:
L1 data cache decomposition for energy efficiency.
ISLPED 2001: 10-15 |
3 | EE | Michael C. Huang,
Jose Renau,
Seung-Moon Yoo,
Josep Torrellas:
The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management.
J. Instruction-Level Parallelism 3: (2001) |
2000 |
2 | EE | Michael C. Huang,
Jose Renau,
Seung-Moon Yoo,
Josep Torrellas:
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips.
Intelligent Memory Systems 2000: 152-159 |
1 | EE | Michael C. Huang,
Jose Renau,
Seung-Moon Yoo,
Josep Torrellas:
A framework for dynamic energy efficiency and temperature management.
MICRO 2000: 202-213 |