| 2008 |
|---|
| 13 | EE | Makoto Sugihara:
SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems.
ISQED 2008: 757-762 |
| 12 | EE | Makoto Sugihara,
Tohru Ishihara,
Kazuaki Murakami:
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems.
IEICE Transactions 91-C(4): 410-417 (2008) |
| 2007 |
|---|
| 11 | EE | Makoto Sugihara,
Tohru Ishihara,
Kazuaki Murakami:
Task scheduling for reliable cache architectures of multiprocessor systems.
DATE 2007: 1490-1495 |
| 10 | EE | Makoto Sugihara,
Tohru Ishihara,
Kazuaki Murakami:
Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems.
IEICE Transactions 90-C(10): 1983-1991 (2007) |
| 9 | EE | Makoto Sugihara,
Kenta Nakamura,
Yusuke Matsunaga,
Kazuaki Murakami:
Technology Mapping Technique for Increasing Throughput of Character Projection Lithography.
IEICE Transactions 90-C(5): 1012-1020 (2007) |
| 2006 |
|---|
| 8 | EE | Makoto Sugihara,
Taiga Takata,
Kenta Nakamura,
Ryoichi Inanami,
Hiroaki Hayashi,
Katsumi Kishimoto,
Tetsuya Hasebe,
Yukihiro Kawano,
Yusuke Matsunaga,
Kazuaki Murakami,
Katsuya Okumura:
A character size optimization technique for throughput enhancement of character projection lithography.
ISCAS 2006 |
| 7 | EE | Makoto Sugihara,
Tohru Ishihara,
Masanori Muroyama,
Koji Hashimoto:
A Simulation-Based Soft Error Estimation Methodology for Computer Systems.
ISQED 2006: 196-203 |
| 6 | EE | Makoto Sugihara,
Taiga Takata,
Kenta Nakamura,
Ryoichi Inanami,
Hiroaki Hayashi,
Katsumi Kishimoto,
Tetsuya Hasebe,
Yukihiro Kawano,
Yusuke Matsunaga,
Kazuaki Murakami,
Katsuya Okumura:
Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment.
IEICE Transactions 89-C(3): 377-383 (2006) |
| 2004 |
|---|
| 5 | EE | Makoto Sugihara,
Kazuaki Murakami,
Yusuke Matsunaga:
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints.
ISVLSI 2004: 179-186 |
| 2002 |
|---|
| 4 | EE | Makoto Sugihara,
Hiroto Yasuura:
Optimization of Test Accesses with a Combined BIST and External Test Scheme.
VLSI Design 2002: 683-688 |
| 2000 |
|---|
| 3 | EE | Makoto Sugihara,
Hiroto Yasuura,
Hiroshi Date:
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach.
DATE 2000: 134-140 |
| 2 | | Hiroshi Date,
Vikram Iyengar,
Krishnendu Chakrabarty,
Makoto Sugihara:
Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores.
PDPTA 2000 |
| 1998 |
|---|
| 1 | EE | Makoto Sugihara,
Hiroshi Date,
Hiroto Yasuura:
A novel test methodology for core-based system LSIs and a testing time minimization problem.
ITC 1998: 465- |
