| 2008 |
|---|
| 7 | EE | Taro Niiyama,
Piao Zhe,
Koichi Ishida,
Masami Murakata,
Makoto Takamiya,
Takayasu Sakurai:
Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators.
ISLPED 2008: 117-122 |
| 6 | EE | Taro Niiyama,
Piao Zhe,
Koichi Ishida,
Masami Murakata,
Makoto Takamiya,
Takayasu Sakurai:
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM.
ISQED 2008: 133-136 |
| 2006 |
|---|
| 5 | EE | Yukihito Oowaki,
Shinichiro Shiratake,
Toshihide Fujiyoshi,
Mototsugu Hamada,
Fumitoshi Hatori,
Masami Murakata,
Masafumi Takahashi:
Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI.
IEICE Transactions 89-C(3): 263-270 (2006) |
| 1998 |
|---|
| 4 | | Takeshi Kitahara,
Fumihiro Minami,
Toshiaki Ueda,
Kimiyoshi Usami,
Seiichi Nishio,
Masami Murakata,
Takashi Mitsuhashi:
A Clock-Gating Method for Low-Power LSI Design.
ASP-DAC 1998: 307-312 |
| 1997 |
|---|
| 3 | EE | Masako Murofushi,
Takashi Ishioka,
Masami Murakata,
Takashi Mitsuhashi:
Layout Driven Re-synthesis for Low Power Consumption LSIs.
DAC 1997: 666-669 |
| 1996 |
|---|
| 2 | EE | Taku Uchino,
Fumihiro Minami,
Masami Murakata,
Takashi Mitsuhashi:
Switching activity analysis for sequential circuits using Boolean approximation method.
ISLPED 1996: 79-84 |
| 1995 |
|---|
| 1 | EE | T. Aoki,
Masami Murakata,
Takashi Mitsuhashi,
Nobuyuki Goto:
Fanout-tree restructuring algorithm for post-placement timing optimization.
ASP-DAC 1995 |
