| 2009 |
|---|
| 10 | EE | Dhruva Ghai,
Saraju P. Mohanty,
Elias Kougianos,
Priyadarsan Patra:
A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS.
ISQED 2009: 47-54 |
| 2008 |
|---|
| 9 | EE | Kaiyu Chen,
Sharad Malik,
Priyadarsan Patra:
Runtime validation of memory ordering using constraint graph checking.
HPCA 2008: 415-426 |
| 8 | EE | Kaiyu Chen,
Sharad Malik,
Priyadarsan Patra:
Runtime Validation of Transactional Memory Systems.
ISQED 2008: 750-756 |
| 7 | EE | Bin Li,
Li-Shiuan Peh,
Priyadarsan Patra:
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration.
NOCS 2008: 117-126 |
| 2007 |
|---|
| 6 | EE | Priyadarsan Patra:
On the cusp of a validation wall.
IEEE Design & Test of Computers 24(2): 193-196 (2007) |
| 2003 |
|---|
| 5 | EE | Kavel M. Büyüksahin,
Priyadarsan Patra,
Farid N. Najm:
ESTIMA: an architectural-level power estimator for multi-ported pipelined register files.
ISLPED 2003: 294-297 |
| 1997 |
|---|
| 4 | EE | Priyadarsan Patra,
Stanislav Polonsky,
Donald S. Fussell:
Delay Insensitive Logic for RSFQ Superconductor Technology.
ASYNC 1997: 42-53 |
| 1996 |
|---|
| 3 | EE | Priyadarsan Patra,
Donald S. Fussell:
Efficient Delay-Insensitive RSFQ Circuits.
ICCD 1996: 413-418 |
| 1995 |
|---|
| 2 | EE | Priyadarsan Patra,
Donald S. Fussell:
Power-efficient delay-insensitive codes for data transmission.
HICSS (1) 1995: 316-323 |
| 1 | EE | Priyadarsan Patra,
Donald S. Fussell:
Fully asynchronous, robust, high-throughput arithmetic structures.
VLSI Design 1995: 141-145 |
