Subramanian Rajagopalan

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

11EESubramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala: Efficient Analog/RF Layout Closure with Compaction Based Legalization. VLSI Design 2009: 137-142
10EESambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy: On Efficient and Robust Constraint Generation for Practical Layout Legalization. ISQED 2008: 379-384
9EEShabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy: Cell Swapping Based Migration Methodology for Analog and Custom Layouts. ISQED 2008: 450-455
8EESubramanian Rajagopalan, Shabbir H. Batterywala: A 3-dimensional FEM Based Resistance Extraction. VLSI Design 2007: 565-570
7EEDebjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou: Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880
6EEWei Qin, Subramanian Rajagopalan, Sharad Malik: A formal concurrency model based architecture description language for synthesis of software development tools. LCTES 2004: 47-56
5EEWei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh: Design Tools for Application Specific Embedded Processors. EMSOFT 2002: 319-333
4 Subramanian Rajagopalan, Sharad Malik: Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors. The Compiler Design Handbook 2002: 603-630
3EEGuilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik: Optimal Live Range Merge for Address Register Allocation in Embedded Programs. CC 2001: 274-288
2EESubramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama: A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1319-1328 (2001)
1EESubramanian Rajagopalan, Manish Vachharajani, Sharad Malik: Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. CASES 2000: 157-164

Coauthor Index

1Guido Araujo [2] [3]
2David I. August [5]
3Shabbir H. Batterywala [7] [8] [9] [10] [11]
4Sambuddha Bhattacharya [9] [10] [11]
5Kurt Keutzer [5]
6Jianfeng Luo [7]
7Hi-Keung Tony Ma [9] [10]
8Sharad Malik [1] [2] [3] [4] [5] [6]
9Guilherme Ottoni [3]
10Li-Shiuan Peh [5]
11Wei Qin [5] [6]
12Sreeranga P. Rajan [2]
13Sandro Rigo [2] [3]
14Narendra V. Shenoy [7] [9] [10]
15Debjit Sinha [7]
16Koichiro Takayama [2]
17Manish Vachharajani [1] [5]
18Hangsheng Wang [5]
19Hai Zhou [7]
20Xinping Zhu [5]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)