| 2009 |
|---|
| 11 | EE | Subramanian Rajagopalan,
Sambuddha Bhattacharya,
Shabbir H. Batterywala:
Efficient Analog/RF Layout Closure with Compaction Based Legalization.
VLSI Design 2009: 137-142 |
| 2008 |
|---|
| 10 | EE | Sambuddha Bhattacharya,
Shabbir H. Batterywala,
Subramanian Rajagopalan,
Hi-Keung Tony Ma,
Narendra V. Shenoy:
On Efficient and Robust Constraint Generation for Practical Layout Legalization.
ISQED 2008: 379-384 |
| 9 | EE | Shabbir H. Batterywala,
Sambuddha Bhattacharya,
Subramanian Rajagopalan,
Hi-Keung Tony Ma,
Narendra V. Shenoy:
Cell Swapping Based Migration Methodology for Analog and Custom Layouts.
ISQED 2008: 450-455 |
| 2007 |
|---|
| 8 | EE | Subramanian Rajagopalan,
Shabbir H. Batterywala:
A 3-dimensional FEM Based Resistance Extraction.
VLSI Design 2007: 565-570 |
| 7 | EE | Debjit Sinha,
Jianfeng Luo,
Subramanian Rajagopalan,
Shabbir H. Batterywala,
Narendra V. Shenoy,
Hai Zhou:
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.
VLSI Design 2007: 875-880 |
| 2004 |
|---|
| 6 | EE | Wei Qin,
Subramanian Rajagopalan,
Sharad Malik:
A formal concurrency model based architecture description language for synthesis of software development tools.
LCTES 2004: 47-56 |
| 2002 |
|---|
| 5 | EE | Wei Qin,
Subramanian Rajagopalan,
Manish Vachharajani,
Hangsheng Wang,
Xinping Zhu,
David I. August,
Kurt Keutzer,
Sharad Malik,
Li-Shiuan Peh:
Design Tools for Application Specific Embedded Processors.
EMSOFT 2002: 319-333 |
| 4 | | Subramanian Rajagopalan,
Sharad Malik:
Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors.
The Compiler Design Handbook 2002: 603-630 |
| 2001 |
|---|
| 3 | EE | Guilherme Ottoni,
Sandro Rigo,
Guido Araujo,
Subramanian Rajagopalan,
Sharad Malik:
Optimal Live Range Merge for Address Register Allocation in Embedded Programs.
CC 2001: 274-288 |
| 2 | EE | Subramanian Rajagopalan,
Sreeranga P. Rajan,
Sharad Malik,
Sandro Rigo,
Guido Araujo,
Koichiro Takayama:
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1319-1328 (2001) |
| 2000 |
|---|
| 1 | EE | Subramanian Rajagopalan,
Manish Vachharajani,
Sharad Malik:
Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints.
CASES 2000: 157-164 |
