| 2009 |
|---|
| 7 | EE | Leomar S. da Rosa Jr.,
Felipe Ribeiro Schneider,
Renato P. Ribas,
André Inácio Reis:
Switch level optimization of digital CMOS gate networks.
ISQED 2009: 324-329 |
| 2008 |
|---|
| 6 | EE | Paulo F. Butzen,
Leomar S. da Rosa Jr.,
Erasmo J. D. Chiappetta Filho,
Dionatan S. Moura,
André Inácio Reis,
Renato P. Ribas:
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.
ACM Great Lakes Symposium on VLSI 2008: 407-410 |
| 5 | EE | Tiago Muller Gil Cardoso,
Leomar S. da Rosa Jr.,
Felipe de Souza Marques,
Renato P. Ribas,
André Inácio Reis:
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.
ISQED 2008: 47-52 |
| 2007 |
|---|
| 4 | EE | Felipe S. Marques,
Leomar S. da Rosa Jr.,
Renato P. Ribas,
Sachin S. Sapatnekar,
André Inácio Reis:
DAG based library-free technology mapping.
ACM Great Lakes Symposium on VLSI 2007: 293-298 |
| 3 | EE | Leomar S. da Rosa Jr.,
André Inácio Reis,
Renato P. Ribas,
Felipe de Souza Marques,
Felipe Ribeiro Schneider:
A comparative study of CMOS gates with minimum transistor stacks.
SBCCI 2007: 93-98 |
| 2006 |
|---|
| 2 | EE | Leomar S. da Rosa Jr.,
Felipe S. Marques,
Tiago Muller Gil Cardoso,
Renato P. Ribas,
Sachin S. Sapatnekar,
André Inácio Reis:
Fast disjoint transistor networks from BDDs.
SBCCI 2006: 137-142 |
| 2003 |
|---|
| 1 | EE | Leomar S. da Rosa Jr.,
Flávio Rech Wagner,
Luigi Carro,
Alexandre Carissimi,
André Inácio Reis:
Scheduling Policy Costs on a JAVA Microcontroller.
OTM Workshops 2003: 520-533 |
