Tun Li

2008
17	EE	WanXia Qu, Tun Li, Yang Guo, Xiaodong Yang: Explicit Model Checking Based on Integer Pointer and Fibonacci Hash. ICYCS 2008: 844-849
16	EE	Dan Zhu, Tun Li, Yang Guo, Sikun Li: 2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions. ISQED 2008: 637-642
2007
15	EE	Zhihui Xiong, Maojun Zhang, Yunli Wang, Tun Li, Sikun Li: Fast Panorama Unrolling of Catadioptric Omni-Directional Images for Cooperative Robot Vision System. CSCWD 2007: 1100-1104
14	EE	Sikun Li, Dawei Wang, Tun Li, Yong Dou: Distributed Collaborative Partition Method of Reconfigurable SoC Using Ant Colony Optimization. CSCWD 2007: 133-138
13	EE	Tun Li, Sikun Li, Jinshan Yu, Yang Guo: A Novel Collaborative Verification Environment for SoC Co-Verification. CSCWD 2007: 145-150
2006
12	EE	Jinshan Yu, Tun Li, Yang Guo, QingPing Tan: Scheduling of Transactions Based on Extended Scheduling Timed Petri Nets for SoC System-Level Test-Case Generation. EUC 2006: 732-741
2005
11	EE	Tun Li, Dan Zhu, Lei Liang, Yang Guo, Sikun Li: Automatic functional test program generation for microprocessor verification. ASP-DAC 2005: 1039-1042
10	EE	Tun Li, Yang Guo, Sikun Li, GongJie Liu: Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming. ATVA 2005: 174-186
9	EE	Tun Li, Yang Guo, GongJie Liu, Sikun Li: Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming. DSD 2005: 17-25
8	EE	Tun Li, Dan Zhu, Yang Guo, GongJie Liu, Sikun Li: MA2TG: A Functional Test Program Generator for Microprocessor Verification. DSD 2005: 176-183
7	EE	Tun Li, Yang Guo, Sikun Li, Dan Zhu: Applying Constraint Logic Programming to Predicate Abstraction of RTL Verilog Descriptions. MICAI 2005: 175-184
2004
6	EE	Tun Li, Yang Guo, Sikun Li: Assertion-based automated functional vectors generation using constraint logic programming. ACM Great Lakes Symposium on VLSI 2004: 288-291
5	EE	Tun Li, Yang Guo, Sikun Li, FuJiang Ao, GongJie Li: Parallel verilog simulation: architecture and circuit partition. ASP-DAC 2004: 644-646
4	EE	Tun Li, Yang Guo, Sikun Li: CLP Based Static Property Checking. ATVA 2004: 495-498
3	EE	Tun Li, Yang Guo, Sikun Li: Design and Implementation of a Parallel Verilog Simulator: PVSim. VLSI Design 2004: 329-334
2	EE	Tun Li, Yang Guo, Sikun Li: Automatic Circuit Extractor for HDL Description Using Program Slicing. J. Comput. Sci. Technol. 19(5): 718-728 (2004)
2003
1	EE	Tun Li, Yang Guo, Sikun Li: An Automatic Circuit Extractor for RTL Verification. Asian Test Symposium 2003: 154-160

Coauthor Index

1	FuJiang Ao	[5]
2	Yong Dou	[14]
3	Yang Guo	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [16] [17]
4	GongJie Li	[5]
5	Sikun Li	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] [16]
6	Lei Liang	[11]
7	GongJie Liu	[8] [9] [10]
8	WanXia Qu	[17]
9	QingPing Tan	[12]
10	Dawei Wang	[14]
11	Yunli Wang	[15]
12	Zhihui Xiong	[15]
13	Xiaodong Yang	[17]
14	Jinshan Yu	[12] [13]
15	Maojun Zhang	[15]
16	Dan Zhu	[7] [8] [11] [16]