| 2008 |
|---|
| 10 | EE | Mohammad Hosseinabady,
Mohammad Reza Kakoee,
Jimson Mathew,
Dhiraj K. Pradhan:
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs.
DATE 2008: 1370-1373 |
| 9 | EE | Mohammad Reza Kakoee,
Mohammad Riazati,
Siamak Mohammadi:
Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions.
ISQED 2008: 230-235 |
| 8 | EE | Mohammad Reza Kakoee,
Mohammad Hossein Neishaburi,
Siamak Mohammadi:
Graph based test case generation for TLM functional verification.
Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 288-295 (2008) |
| 2007 |
|---|
| 7 | EE | Mohammad Hossein Neishaburi,
Masoud Daneshtalab,
Mohammad Reza Kakoee,
Saeed Safari:
Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors.
AICCSA 2007: 528-534 |
| 6 | | Mohammad Hossein Neishaburi,
Mohammad Reza Kakoee,
Masoud Daneshtalab,
Saeed Safari,
Zainalabedin Navabi:
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.
DDECS 2007: 247-250 |
| 5 | EE | Mohammad Reza Kakoee,
Mohammad Hossein Neishaburi,
Siamak Mohammadi:
Functional Test-Case Generation by a Control Transaction Graph for TLM Verification.
DSD 2007: 157-164 |
| 4 | EE | Mohammad Reza Kakoee,
Mohammad Hossein Neishaburi,
Masoud Daneshtalab,
Saeed Safari,
Zainalabedin Navabi:
On-Chip Verification of NoCs Using Assertion Processors.
DSD 2007: 535-538 |
| 3 | EE | Mohammad Reza Kakoee,
Hamid Shojaei,
Hassan Ghasemzadeh,
Marjan Sirjani,
Zainalabedin Navabi:
A New Approach for Design and Verification of Transaction Level Models.
ISCAS 2007: 3760-3763 |
| 2006 |
|---|
| 2 | EE | Hassan Ghasemzadeh,
Sepideh Sepideh Mazrouee,
Mohammad Reza Kakoee:
Modified Pseudo LRU Replacement Algorithm.
ECBS 2006: 368-376 |
| 2003 |
|---|
| 1 | EE | Bijan Alizadeh,
Mohammad Reza Kakoee:
Using Integer Equations for High Level Formal Verification Property Checking.
ISQED 2003: 69-74 |
