2008 |
12 | EE | Saibal Mukhopadhyay,
Rahul M. Rao,
Jae-Joon Kim,
Ching-Te Chuang:
Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies.
ISCAS 2008: 384-387 |
11 | EE | Amlan Ghosh,
Rahul M. Rao,
Ching-Te Chuang,
Richard B. Brown:
On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits.
ISQED 2008: 815-820 |
10 | EE | Amlan Ghosh,
Rahul M. Rao,
Jae-Joon Kim,
Ching-Te Chuang,
Richard B. Brown:
On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit.
VLSI Design 2008: 143-149 |
2007 |
9 | EE | Kanak Agarwal,
Rahul M. Rao,
Dennis Sylvester,
Richard B. Brown:
Parametric Yield Analysis and Optimization in Leakage Dominated Technologies.
IEEE Trans. VLSI Syst. 15(6): 613-623 (2007) |
2005 |
8 | EE | Rahul M. Rao,
Kanak Agarwal,
Dennis Sylvester,
Himanshu Kaul,
Richard B. Brown,
Sani R. Nassif:
Power-aware global signaling strategies.
ISCAS (1) 2005: 604-607 |
7 | EE | Rahul M. Rao,
Kanak Agarwal,
Anirudh Devgan,
Kevin J. Nowka,
Dennis Sylvester,
Richard B. Brown:
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization.
ISQED 2005: 284-290 |
6 | EE | Harmander Deogun,
Rahul M. Rao,
Dennis Sylvester,
Richard B. Brown,
Kevin J. Nowka:
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.
ISQED 2005: 88-93 |
2004 |
5 | EE | Rahul M. Rao,
Kanak Agarwal,
Dennis Sylvester,
Richard B. Brown,
Kevin J. Nowka,
Sani R. Nassif:
Approaches to run-time and standby mode leakage reduction in global buses.
ISLPED 2004: 188-193 |
4 | EE | Rahul M. Rao,
Jeffrey L. Burns,
Richard B. Brown:
Analysis and Optimization of Enhanced MTCMOS Scheme.
VLSI Design 2004: 234-239 |
2003 |
3 | EE | Rahul M. Rao,
Frank Liu,
Jeffrey L. Burns,
Richard B. Brown:
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits.
ICCAD 2003: 689-692 |
2 | EE | Rahul M. Rao,
Jeffrey L. Burns,
Anirudh Devgan,
Richard B. Brown:
Efficient techniques for gate leakage estimation.
ISLPED 2003: 100-103 |
1 | EE | Emrah Acar,
Anirudh Devgan,
Rahul M. Rao,
Ying Liu,
Haihua Su,
Sani R. Nassif,
Jeffrey L. Burns:
Leakage and leakage sensitivity computation for combinational circuits.
ISLPED 2003: 96-99 |