| 2008 |
|---|
| 9 | EE | Shervin Sharifi,
Tajana Simunic Rosing:
An analytical model for the upper bound on temperature differences on a chip.
ACM Great Lakes Symposium on VLSI 2008: 417-422 |
| 8 | EE | Shervin Sharifi,
Chunchen Liu,
Tajana Simunic Rosing:
Accurate Temperature Estimation for Efficient Thermal Management.
ISQED 2008: 137-142 |
| 7 | EE | Mohammad Hosseinabady,
Shervin Sharifi,
Fabrizio Lombardi,
Zainalabedin Navabi:
A Selective Trigger Scan Architecture for VLSI Testing.
IEEE Trans. Computers 57(3): 316-328 (2008) |
| 2007 |
|---|
| 6 | EE | Shervin Sharifi,
Javid Jaffari,
Mohammad Hosseinabady,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
CoRR abs/0710.4653: (2007) |
| 2006 |
|---|
| 5 | EE | Shervin Sharifi,
Javid Jaffari,
Mohammad Hosseinabady,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Scan-Based Structure with Reduced Static and Dynamic Power Consumption.
J. Low Power Electronics 2(3): 477-487 (2006) |
| 2005 |
|---|
| 4 | EE | Shervin Sharifi,
Javid Jaffari,
Mohammad Hosseinabady,
Ali Afzali-Kusha,
Zainalabedin Navabi:
Simultaneous Reduction of Dynamic and Static Power in Scan Structures.
DATE 2005: 846-851 |
| 3 | EE | Safar Hatami,
Shervin Sharifi,
Mahmoud Kamarei,
Hossein Ahmadi:
Real-time image compression based on wavelet vector quantization, algorithm and VLSI architecture.
ISCAS (3) 2005: 2381-2384 |
| 2003 |
|---|
| 2 | EE | Shervin Sharifi,
Mohammad Hosseinabady,
Pedram A. Riahi,
Zainalabedin Navabi:
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.
DFT 2003: 352-360 |
| 1 | | Shervin Sharifi,
Mohammad Hosseinabady,
Zainalabedin Navabi:
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing.
VLSI-SOC 2003: 215-220 |
