| 2008 |
|---|
| 8 | EE | Chittarsu Raghunandan,
K. S. Sainarayanan,
M. B. Srinivas:
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.
ISQED 2008: 43-46 |
| 2007 |
|---|
| 7 | EE | Chittarsu Raghunandan,
K. S. Sainarayanan,
M. B. Srinivas:
Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.
ACM Great Lakes Symposium on VLSI 2007: 371-376 |
| 6 | EE | Chittarsu Raghunandan,
K. S. Sainarayanan,
M. B. Srinivas:
Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN).
ISCAS 2007: 1129-1132 |
| 5 | EE | K. S. Sainarayanan,
Chittarsu Raghunandan,
M. B. Srinivas:
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme.
ISVLSI 2007: 401-408 |
| 4 | EE | K. S. Sainarayanan,
Chittarsu Raghunandan,
M. B. Srinivas:
Bus encoding schemes for minimizing delay in VLSI interconnects.
SBCCI 2007: 184-189 |
| 2006 |
|---|
| 3 | EE | K. S. Sainarayanan,
J. V. R. Ravindra,
M. B. Srinivas:
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method.
DELTA 2006: 336-339 |
| 2 | EE | K. S. Sainarayanan,
J. V. R. Ravindra,
M. B. Srinivas:
A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.
ISCAS 2006 |
| 2005 |
|---|
| 1 | | K. S. Sainarayanan,
J. V. R. Ravindra,
M. B. Srinivas:
A novel deep submicron low power bus coding technique.
Circuits, Signals, and Systems 2005: 154-159 |
