2009 |
18 | EE | Leomar S. da Rosa Jr.,
Felipe Ribeiro Schneider,
Renato P. Ribas,
André Inácio Reis:
Switch level optimization of digital CMOS gate networks.
ISQED 2009: 324-329 |
2008 |
17 | EE | Paulo F. Butzen,
Leomar S. da Rosa Jr.,
Erasmo J. D. Chiappetta Filho,
Dionatan S. Moura,
André Inácio Reis,
Renato P. Ribas:
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.
ACM Great Lakes Symposium on VLSI 2008: 407-410 |
16 | EE | Tiago Muller Gil Cardoso,
Leomar S. da Rosa Jr.,
Felipe de Souza Marques,
Renato P. Ribas,
André Inácio Reis:
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.
ISQED 2008: 47-52 |
2007 |
15 | EE | Paulo F. Butzen,
André Inácio Reis,
Chris H. Kim,
Renato P. Ribas:
Modeling and estimating leakage current in series-parallel CMOS networks.
ACM Great Lakes Symposium on VLSI 2007: 269-274 |
14 | EE | Felipe S. Marques,
Leomar S. da Rosa Jr.,
Renato P. Ribas,
Sachin S. Sapatnekar,
André Inácio Reis:
DAG based library-free technology mapping.
ACM Great Lakes Symposium on VLSI 2007: 293-298 |
13 | EE | Paulo F. Butzen,
André Inácio Reis,
Chris H. Kim,
Renato P. Ribas:
Modeling Subthreshold Leakage Current in General Transistor Networks.
ISVLSI 2007: 512-513 |
12 | EE | Paulo F. Butzen,
André Inácio Reis,
Chris H. Kim,
Renato P. Ribas:
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates.
PATMOS 2007: 474-484 |
11 | EE | Leomar S. da Rosa Jr.,
André Inácio Reis,
Renato P. Ribas,
Felipe de Souza Marques,
Felipe Ribeiro Schneider:
A comparative study of CMOS gates with minimum transistor stacks.
SBCCI 2007: 93-98 |
2006 |
10 | EE | Leomar S. da Rosa Jr.,
Felipe S. Marques,
Tiago Muller Gil Cardoso,
Renato P. Ribas,
Sachin S. Sapatnekar,
André Inácio Reis:
Fast disjoint transistor networks from BDDs.
SBCCI 2006: 137-142 |
9 | EE | R. U. R. Mocho,
G. H. Sartori,
Renato P. Ribas,
André Inácio Reis:
Asynchronous circuit design on reconfigurable devices.
SBCCI 2006: 20-25 |
2005 |
8 | EE | Felipe S. Marques,
Renato P. Ribas,
Sachin S. Sapatnekar,
André Inácio Reis:
A new approach to the use of satisfiability in false path detection.
ACM Great Lakes Symposium on VLSI 2005: 308-311 |
7 | EE | João Daniel Togni,
Renato P. Ribas,
Maria Lúcia Blanck Lisbôa,
André Inácio Reis:
Tool integration using the web-services approach.
ACM Great Lakes Symposium on VLSI 2005: 337-340 |
6 | EE | Felipe Ribeiro Schneider,
Renato P. Ribas,
Sachin S. Sapatnekar,
André Inácio Reis:
Exact lower bound for the number of switches in series to implement a combinational logic cell.
ICCD 2005: 357-362 |
2004 |
5 | EE | Mário C. B. Osorio,
Carlos A. Sampaio,
André Inácio Reis,
Renato P. Ribas:
Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic.
SBCCI 2004: 181-185 |
2003 |
4 | EE | Renato E. B. Poli,
Felipe Ribeiro Schneider,
Renato P. Ribas,
André Inácio Reis:
Unified Theory to Build Cell-Level Transistor Networks from BDDs.
SBCCI 2003: 199-204 |
2002 |
3 | | Felipe Ribeiro Schneider,
Vinícius P. Correia,
Renato P. Ribas,
André Inácio Reis:
Comparing Transistor-Level Implementations of 4-Input Logic Functions.
IWLS 2002: 361-365 |
2001 |
2 | EE | Renato P. Ribas,
F. R. Barbosa,
N. Turatti:
Integrated Circuits Design Teaching Using Professional CAD Environments.
MSE 2001: 77- |
1 | | Renato P. Ribas,
André Inácio Reis,
Marcelo Lubaszewski:
Concepção de Circuitos e Sistemas Integrados.
RITA 8(1): 7-21 (2001) |