dblp.uni-trier.dewww.uni-trier.de

Vijay Sundararajan

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2008
15EEVijay Sundararajan: Gate Sizing. Encyclopedia of Algorithms 2008
2004
14EEVijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints. ACM Trans. Design Autom. Electr. Syst. 9(3): 273-289 (2004)
2002
13EEVijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: Fast and exact transistor sizing based on iterative relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 568-581 (2002)
2001
12EEImed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi: Energy efficient signaling in DSM CMOS technology. ISCAS (5) 2001: 411-414
11EEImed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi: Energy Efficient Signaling in Deep Submicron CMOS Technology. ISQED 2001: 319-324
10EEMichael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi: Vector processing of wavelet coefficients for robust image denoising. Image Vision Comput. 19(7): 435-450 (2001)
2000
9EEVijay Sundararajan, Keshab K. Parhi: Reducing bus transition activity by limited weight coding with codeword slimming. ACM Great Lakes Symposium on VLSI 2000: 13-16
8EEVijay Sundararajan, Keshab K. Parhi: Synthesis of low power folded programmable coefficient FIR digital filters (short paper). ASP-DAC 2000: 153-156
7EEVijay Sundararajan, Keshab K. Parhi: Data transmission over a bus with peak-limited transition activity. ASP-DAC 2000: 221-224
6EEVijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: MINFLOTRANSIT: min-cost flow based transistor sizing tool. DAC 2000: 649-664
1999
5EEVijay Sundararajan, Keshab K. Parhi: Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution. ARVLSI 1999: 170-185
4EEVijay Sundararajan, Keshab K. Parhi: Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages. DAC 1999: 72-75
3EEVijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi: Marsh: min-area retiming with setup and hold constraints. ICCAD 1999: 2-6
2EEVijay Sundararajan, Keshab K. Parhi: Low power synthesis of dual threshold voltage CMOS VLSI circuits. ISLPED 1999: 139-144
1997
1EEMichael E. Zervakis, Vijay Sundararajan, Keshab K. Parhi: A Wavelet-Domain Algorithm for Denoising in the Presence of Noise Outliers. ICIP (1) 1997: 632-635

Coauthor Index

1Imed Ben Dhaou [11] [12]
2Keshab K. Parhi [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
3Sachin S. Sapatnekar [3] [6] [13] [14]
4Hannu Tenhunen [11] [12]
5Michael E. Zervakis [1] [10]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)