| 2002 |
|---|
| 12 | EE | Keerthi Heragu,
Manish Sharma,
Rahul Kundu,
Ronald D. Blanton:
Test vector generation for charge sharing failures in dynamic logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1502-1508 (2002) |
| 2001 |
|---|
| 11 | EE | Keerthi Heragu,
Manish Sharma,
Rahul Kundu,
R. D. (Shawn) Blanton:
Testing of Dynamic Logic Circuits Based on Charge Sharing.
VTS 2001: 396-403 |
| 1999 |
|---|
| 10 | EE | Keerthi Heragu,
Janak H. Patel,
Vishwani D. Agrawal:
A Test Generator for Segment Delay Faults.
VLSI Design 1999: 484-491 |
| 1998 |
|---|
| 9 | EE | Keerthi Heragu:
Where We Might Stumble with Embedded-System Test.
VTS 1998: 470 |
| 1997 |
|---|
| 8 | EE | Keerthi Heragu,
Janak H. Patel,
Vishwani D. Agrawal:
Fast identification of untestable delay faults using implications.
ICCAD 1997: 642-647 |
| 7 | EE | Keerthi Heragu,
Vishwani D. Agrawal,
Michael L. Bushnell,
Janak H. Patel:
Improving a nonenumerative method to estimate path delay fault coverage.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 759-762 (1997) |
| 1996 |
|---|
| 6 | EE | Keerthi Heragu,
Janak H. Patel,
Vishwani D. Agrawal:
SIGMA: a simulator for segment delay faults.
ICCAD 1996: 502-508 |
| 5 | EE | Keerthi Heragu,
Janak H. Patel,
Vishwani D. Agrawal:
Improving accuracy in path delay fault coverage estimation.
VLSI Design 1996: 422-425 |
| 4 | EE | Keerthi Heragu,
Janak H. Patel,
Vishwani D. Agrawal:
Segment delay faults: a new fault model.
VTS 1996: 32-41 |
| 1995 |
|---|
| 3 | EE | Keerthi Heragu,
Vishwani D. Agrawal,
Michael L. Bushnell:
Statistical methods for delay fault coverage analysis.
VLSI Design 1995: 166-170 |
| 2 | EE | Keerthi Heragu,
Vishwani D. Agrawal,
Michael L. Bushnell:
Fault coverage estimation by test vector sampling.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 590-596 (1995) |
| 1994 |
|---|
| 1 | EE | Keerthi Heragu,
Michael L. Bushnell,
Vishwani D. Agrawal:
An Efficient Path Delay Fault Coverage Estimator.
DAC 1994: 516-521 |
