| 2008 |
|---|
| 138 | EE | Daesun Oh,
Keshab K. Parhi:
Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes.
ACM Great Lakes Symposium on VLSI 2008: 451-456 |
| 137 | EE | Renfei Liu,
Keshab K. Parhi:
Fast composite field S-box architectures for advanced encryption standard.
ACM Great Lakes Symposium on VLSI 2008: 65-70 |
| 136 | EE | Daesun Oh,
Keshab K. Parhi:
Area efficient controller design of barrel shifters for reconfigurable LDPC decoders.
ISCAS 2008: 240-243 |
| 135 | EE | Chao Cheng,
Keshab K. Parhi:
High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform.
IEEE Transactions on Signal Processing 56(1): 393-403 (2008) |
| 2007 |
|---|
| 134 | EE | Daesun Oh,
Keshab K. Parhi:
Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes.
ISCAS 2007: 1855-1858 |
| 133 | EE | Yuping Zhang,
Keshab K. Parhi:
Parallel Architecture of List Sphere Decoders.
ISCAS 2007: 2096-2099 |
| 132 | EE | Daesun Oh,
Keshab K. Parhi:
Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes.
ISCAS 2007: 2758-2761 |
| 131 | EE | Yongru Gu,
Keshab K. Parhi:
Pipelined Parallel Decision-Feedback Decoders for High-Speed Ethernet Over Copper.
IEEE Transactions on Signal Processing 55(2): 707-715 (2007) |
| 2006 |
|---|
| 130 | EE | Daesun Oh,
Keshab K. Parhi:
Low Complexity Design of High Speed Parallel Decision Feedback Equalizers.
ASAP 2006: 118-124 |
| 129 | EE | Aaron E. Cohen,
Keshab K. Parhi:
Faster elliptic curve point multiplication based on a novel greedy base-2, 3 method.
ISCAS 2006 |
| 128 | EE | Jian-Hung Lin,
Keshab K. Parhi:
Low complexity block turbo equalization.
ISCAS 2006 |
| 127 | EE | Chao Cheng,
Keshab K. Parhi:
Hardware Efficient Fast Computation of the Discrete Fourier Transform.
VLSI Signal Processing 42(2): 159-171 (2006) |
| 126 | EE | Yongru Gu,
Keshab K. Parhi:
Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper.
VLSI Signal Processing 42(3): 211-221 (2006) |
| 125 | EE | Chao Cheng,
Keshab K. Parhi:
Hardware efficient fast computation of the discrete fourier transform.
VLSI Signal Processing 43(1): 105-106 (2006) |
| 124 | EE | Lijun Gao,
Keshab K. Parhi:
Models for Architectural Power and Power Grid Noise Analysis on Data Bus.
VLSI Signal Processing 44(1-2): 25-46 (2006) |
| 2005 |
|---|
| 123 | EE | Yongru Gu,
Keshab K. Parhi:
Pipelining Tomlinson-Harashima precoders.
ISCAS (1) 2005: 408-411 |
| 122 | EE | Sang-Min Kim,
Jun Tang,
Keshab K. Parhi:
Quasi-cyclic low-density parity-check coded multi-band-OFDM UWB systems.
ISCAS (1) 2005: 65-68 |
| 121 | EE | Chao Cheng,
Keshab K. Parhi:
Further complexity reduction of parallel FIR filters.
ISCAS (2) 2005: 1835-1838 |
| 120 | EE | Jian-Hung Lin,
Keshab K. Parhi:
VLSI architectures for stereoscopic video disparity matching and object extraction.
ISCAS (3) 2005: 2373-2376 |
| 119 | EE | Xinmiao Zhang,
Keshab K. Parhi:
Fast factorization architecture in soft-decision Reed-Solomon decoding.
IEEE Trans. VLSI Syst. 13(4): 413-426 (2005) |
| 118 | EE | Keshab K. Parhi:
Design of multigigabit multiplexer-loop-based decision feedback equalizers.
IEEE Trans. VLSI Syst. 13(4): 489-493 (2005) |
| 117 | EE | Xinmiao Zhang,
Keshab K. Parhi:
High-Speed Architectures for Parallel Long BCH Encoders.
IEEE Trans. VLSI Syst. 13(7): 872-877 (2005) |
| 116 | EE | Yanni Chen,
Keshab K. Parhi:
On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes.
VLSI Signal Processing 39(1-2): 35-47 (2005) |
| 115 | EE | Naresh R. Shanbhag,
Keshab K. Parhi:
Guest Editorial.
VLSI Signal Processing 39(1-2): 5-6 (2005) |
| 2004 |
|---|
| 114 | EE | Xinmiao Zhang,
Keshab K. Parhi:
High-speed architectures for parallel long BCH encoders.
ACM Great Lakes Symposium on VLSI 2004: 1-6 |
| 113 | | Keshab K. Parhi:
Novel pipelining of MSB-first add-compare select unit structure for Viterbi decoders.
ISCAS (2) 2004: 501-504 |
| 112 | | Yuping Zhang,
Keshab K. Parhi:
Parallel Turbo decoding.
ISCAS (2) 2004: 509-512 |
| 111 | EE | Chao Cheng,
Keshab K. Parhi:
Hardware efficient fast parallel FIR filter structures based on iterated short convolution.
ISCAS (3) 2004: 361-364 |
| 110 | | Ebrahim Saberinia,
Jun Tang,
Ahmed H. Tewfik,
Keshab K. Parhi:
Pulsed OFDM modulation for ultra wideband communications.
ISCAS (5) 2004: 369-392 |
| 109 | | Jun Tang,
Ahmed H. Tewfik,
Keshab K. Parhi:
High performance solution for interfering UWB piconets with reduced complexity sphere decoding.
ISCAS (5) 2004: 377-380 |
| 108 | EE | Vijay Sundararajan,
Sachin S. Sapatnekar,
Keshab K. Parhi:
A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints.
ACM Trans. Design Autom. Electr. Syst. 9(3): 273-289 (2004) |
| 107 | | Kyung-Ju Cho,
Kwang-Chul Lee,
Jin-Gyun Chung,
Keshab K. Parhi:
Design of low-error fixed-width modified booth multiplier.
IEEE Trans. VLSI Syst. 12(5): 522-531 (2004) |
| 106 | | Yanni Chen,
Keshab K. Parhi:
Small area parallel Chien search architectures for long BCH codes.
IEEE Trans. VLSI Syst. 12(5): 545-549 (2004) |
| 105 | EE | Jun Jin Kong,
Keshab K. Parhi:
Low-latency architectures for high-throughput rate Viterbi decoders.
IEEE Trans. VLSI Syst. 12(6): 642-651 (2004) |
| 104 | EE | Xinmiao Zhang,
Keshab K. Parhi:
High-speed VLSI architectures for the AES algorithm.
IEEE Trans. VLSI Syst. 12(9): 957-967 (2004) |
| 103 | | Zhipei Chi,
Leilei Song,
Keshab K. Parhi:
On The Performance/Complexity Tradeoff in Block Turbo Decoder Design.
IEEE Transactions on Communications 52(2): 173-175 (2004) |
| 102 | EE | Zhipei Chi,
Zhongfeng Wang,
Keshab K. Parhi:
On the better protection of short-frame turbo codes.
IEEE Transactions on Communications 52(9): 1435-1439 (2004) |
| 2003 |
|---|
| 101 | EE | Yanni Chen,
Keshab K. Parhi:
High throughput overlapped message passing for low density parity check codes.
ACM Great Lakes Symposium on VLSI 2003: 245-248 |
| 100 | EE | Ji-Suk Park,
Byeong-Kuk Kim,
Jin-Gyun Chung,
Keshab K. Parhi:
High-speed tunable fractional-delay allpass filter structure.
ISCAS (4) 2003: 165-168 |
| 99 | EE | T. Sansaloni,
Javier Valls,
Keshab K. Parhi:
Digit-Serial Complex-Number Multipliers on FPGAs.
VLSI Signal Processing 33(1-2): 105-115 (2003) |
| 98 | EE | Bibhudatta Sahoo,
Keshab K. Parhi:
A Low Power Correlator for CDMA Wireless Systems.
VLSI Signal Processing 35(1): 105-112 (2003) |
| 97 | EE | Lijun Gao,
Keshab K. Parhi,
Jun Ma:
Relaxed Annihilation-Reordering Look-Ahead QRD-RLS Adaptive Filters.
VLSI Signal Processing 35(2): 119-135 (2003) |
| 2002 |
|---|
| 96 | EE | Tong Zhang,
Keshab K. Parhi:
On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders.
ACM Great Lakes Symposium on VLSI 2002: 89-93 |
| 95 | EE | Sang-Min Kim,
Jin-Gyun Chung,
Keshab K. Parhi:
Design of low error CSD fixed-width multiplier.
ISCAS (1) 2002: 69-72 |
| 94 | EE | Gunok Jung,
Jun Jin Kong,
Gerald E. Sobelman,
Keshab K. Parhi:
High-speed add-compare-select units using locally self-resetting CMOS.
ISCAS (1) 2002: 889-892 |
| 93 | EE | Zhipei Chi,
Keshab K. Parhi:
High speed VLSI architecture design for block turbo decoder.
ISCAS (1) 2002: 901-904 |
| 92 | EE | Zhongfeng Wang,
Zhipei Chi,
Keshab K. Parhi:
Area-efficient high-speed decoding schemes for turbo decoders.
IEEE Trans. VLSI Syst. 10(6): 902-912 (2002) |
| 91 | EE | Vijay Sundararajan,
Sachin S. Sapatnekar,
Keshab K. Parhi:
Fast and exact transistor sizing based on iterative relaxation.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 568-581 (2002) |
| 90 | EE | William L. Freking,
Keshab K. Parhi:
Performance-Scalable Array Architectures for Modular Multiplication.
VLSI Signal Processing 31(2): 101-116 (2002) |
| 89 | EE | Javier Valls,
Martin Kuhlmann,
Keshab K. Parhi:
Evaluation of CORDIC Algorithms for FPGA Design.
VLSI Signal Processing 32(3): 207-222 (2002) |
| 2001 |
|---|
| 88 | EE | Lijun Gao,
Keshab K. Parhi:
Models for power consumption and power grid noise due to datapath transition activity.
ACM Great Lakes Symposium on VLSI 2001: 121-126 |
| 87 | EE | Tong Zhang,
Zhongfeng Wang,
Keshab K. Parhi:
On finite precision implementation of low density parity check codes decoder.
ISCAS (4) 2001: 202-205 |
| 86 | EE | Lijun Gao,
Keshab K. Parhi:
Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec.
ISCAS (4) 2001: 574-577 |
| 85 | EE | Zhipei Chi,
Leilei Song,
Keshab K. Parhi:
A study on the performance, complexity tradeoffs of block turbo decoder design.
ISCAS (4) 2001: 65-68 |
| 84 | EE | Imed Ben Dhaou,
Hannu Tenhunen,
Vijay Sundararajan,
Keshab K. Parhi:
Energy efficient signaling in DSM CMOS technology.
ISCAS (5) 2001: 411-414 |
| 83 | EE | Imed Ben Dhaou,
Hannu Tenhunen,
Vijay Sundararajan,
Keshab K. Parhi:
Energy Efficient Signaling in Deep Submicron CMOS Technology.
ISQED 2001: 319-324 |
| 82 | EE | Tong Zhang,
Keshab K. Parhi:
Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials.
IEEE Trans. Computers 50(7): 734-749 (2001) |
| 81 | EE | Michael E. Zervakis,
Vijay Sundararajan,
Keshab K. Parhi:
Vector processing of wavelet coefficients for robust image denoising.
Image Vision Comput. 19(7): 435-450 (2001) |
| 80 | EE | Zhongfeng Wang,
Hiroshi Suzuki,
Keshab K. Parhi:
Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders.
VLSI Signal Processing 29(3): 209-221 (2001) |
| 2000 |
|---|
| 79 | EE | Vijay Sundararajan,
Keshab K. Parhi:
Reducing bus transition activity by limited weight coding with codeword slimming.
ACM Great Lakes Symposium on VLSI 2000: 13-16 |
| 78 | EE | Bibhudatta Sahoo,
Martin Kuhlmann,
Keshab K. Parhi:
A low-power correlator.
ACM Great Lakes Symposium on VLSI 2000: 153-155 |
| 77 | EE | William L. Freking,
Keshab K. Parhi:
Performance-Scalable Array Architectures for Modular Multiplication.
ASAP 2000: 149- |
| 76 | EE | Lijun Gao,
Keshab K. Parhi:
Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power Consumption.
ASAP 2000: 225-234 |
| 75 | EE | Vijay Sundararajan,
Keshab K. Parhi:
Synthesis of low power folded programmable coefficient FIR digital filters (short paper).
ASP-DAC 2000: 153-156 |
| 74 | EE | Vijay Sundararajan,
Keshab K. Parhi:
Data transmission over a bus with peak-limited transition activity.
ASP-DAC 2000: 221-224 |
| 73 | EE | Vijay Sundararajan,
Sachin S. Sapatnekar,
Keshab K. Parhi:
MINFLOTRANSIT: min-cost flow based transistor sizing tool.
DAC 2000: 649-664 |
| 72 | EE | Janardhan H. Satyanarayana,
Keshab K. Parhi:
Power Estimation of Digital Data Paths Using HEAT.
IEEE Design & Test of Computers 17(2): 101-110 (2000) |
| 71 | EE | Janardhan H. Satyanarayana,
Keshab K. Parhi:
Theoretical analysis of word-level switching activity in the presence of glitching and correlation.
IEEE Trans. VLSI Syst. 8(2): 148-159 (2000) |
| 70 | EE | Leilei Song,
Keshab K. Parhi,
Ichiro Kuroda,
Takao Nishitani:
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs.
IEEE Trans. VLSI Syst. 8(2): 160-172 (2000) |
| 69 | EE | Ahmed F. Shalash,
Keshab K. Parhi:
Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications.
VLSI Signal Processing 25(3): 199-213 (2000) |
| 1999 |
|---|
| 68 | EE | Vijay Sundararajan,
Keshab K. Parhi:
Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution.
ARVLSI 1999: 170-185 |
| 67 | EE | Vijay Sundararajan,
Keshab K. Parhi:
Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages.
DAC 1999: 72-75 |
| 66 | EE | Janardhan H. Satyanarayana,
Keshab K. Parhi:
Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation.
Great Lakes Symposium on VLSI 1999: 46-49 |
| 65 | EE | Vijay Sundararajan,
Sachin S. Sapatnekar,
Keshab K. Parhi:
Marsh: min-area retiming with setup and hold constraints.
ICCAD 1999: 2-6 |
| 64 | EE | Martin Kuhlmann,
Sachin S. Sapatnekar,
Keshab K. Parhi:
Efficient Crosstalk Estimation.
ICCD 1999: 266- |
| 63 | EE | William L. Freking,
Keshab K. Parhi:
A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations.
ICCD 1999: 80- |
| 62 | EE | William L. Freking,
Keshab K. Parhi:
Parallel modular multiplication with application to VLSI RSA implementation.
ISCAS (1) 1999: 490-495 |
| 61 | EE | Leilei Song,
Keshab K. Parhi:
Low-complexity modified Mastrovito multipliers over finite fields GF(2M).
ISCAS (1) 1999: 508-512 |
| 60 | EE | Leilei Song,
Keshab K. Parhi:
Low-energy software Reed-Solomon codecs using specialized finite field datapath and division-free Berlekamp-Massey algorithm.
ISCAS (1) 1999: 84-89 |
| 59 | EE | S. Summerfield,
Zhongfeng Wang,
Keshab K. Parhi:
Area-power-time efficient pipeline-interleaved architectures for wave digital filters.
ISCAS (3) 1999: 343-346 |
| 58 | EE | Jun Ma,
Keshab K. Parhi,
Ed F. Deprettere:
Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations.
ISCAS (3) 1999: 347-350 |
| 57 | EE | Zhipei Chi,
Jun Ma,
Keshab K. Parhi:
Pipelined QR decomposition based multi-channel least square lattice adaptive filter architectures.
ISCAS (3) 1999: 49-53 |
| 56 | EE | Ahmed F. Shalash,
Keshab K. Parhi:
Multiple access over wireline channels using orthogonal signaling.
ISCAS (4) 1999: 580-583 |
| 55 | EE | Vijay Sundararajan,
Keshab K. Parhi:
Low power synthesis of dual threshold voltage CMOS VLSI circuits.
ISLPED 1999: 139-144 |
| 54 | EE | Tracy C. Denk,
Keshab K. Parhi:
Two-dimensional retiming [VLSI design].
IEEE Trans. VLSI Syst. 7(2): 198-211 (1999) |
| 53 | EE | Keshab K. Parhi:
Low-energy CSMT carry generators and binary adders.
IEEE Trans. VLSI Syst. 7(4): 450-462 (1999) |
| 52 | EE | Hosahalli R. Srinivas,
Keshab K. Parhi:
A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture.
VLSI Signal Processing 21(1): 37-60 (1999) |
| 1998 |
|---|
| 51 | | Luis A. Montalvo,
Keshab K. Parhi,
Alain Guyot:
New Svoboda-Tung Division.
IEEE Trans. Computers 47(9): 1014-1020 (1998) |
| 50 | EE | S. K. Jain,
Leilei Song,
Keshab K. Parhi:
Efficient semisystolic architectures for finite-field arithmetic.
IEEE Trans. VLSI Syst. 6(1): 101-113 (1998) |
| 49 | EE | K. Ito,
Lori E. Lucke,
Keshab K. Parhi:
ILP-based cost-optimal DSP synthesis with module selection and data format conversion.
IEEE Trans. VLSI Syst. 6(4): 582-594 (1998) |
| 48 | EE | Tracy C. Denk,
Keshab K. Parhi:
Synthesis of folded pipelined architectures for multirate DSP algorithms.
IEEE Trans. VLSI Syst. 6(4): 595-607 (1998) |
| 47 | EE | Keshab K. Parhi,
Valerie Taylor:
Guest Editors' Introduction.
VLSI Signal Processing 19(2): 83 (1998) |
| 46 | EE | Yun-Nan Chang,
Ching-Yi Wang,
Keshab K. Parhi:
Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units.
VLSI Signal Processing 19(3): 243-256 (1998) |
| 1997 |
|---|
| 45 | | Yun-Nan Chang,
Janardhan H. Satyanarayana,
Keshab K. Parhi:
Design and Implementation of Low-Power Digit-Serial Multipliers.
ICCD 1997: 186-195 |
| 44 | | Keshab K. Parhi:
Fast Low-Energy VLSI Binary Addition.
ICCD 1997: 676-684 |
| 43 | EE | Michael E. Zervakis,
Vijay Sundararajan,
Keshab K. Parhi:
A Wavelet-Domain Algorithm for Denoising in the Presence of Noise Outliers.
ICIP (1) 1997: 632-635 |
| 42 | | Hosahalli R. Srinivas,
Keshab K. Parhi,
Luis A. Montalvo:
Radix 2 Division with Over-Redundant Quotient Selection.
IEEE Trans. Computers 46(1): 85-92 (1997) |
| 41 | EE | Keshab K. Parhi,
Takao Nishitani,
Hironori Yamauchi:
Guest Editors' Introduction.
VLSI Signal Processing 16(1): 5-7 (1997) |
| 40 | EE | Kazuhito Ito,
Keshab K. Parhi:
A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis.
VLSI Signal Processing 16(1): 57-72 (1997) |
| 39 | EE | David A. Parker,
Keshab K. Parhi:
Low-Area/Power Parallel FIR Digital Filter Implementations.
VLSI Signal Processing 17(1): 75-92 (1997) |
| 1996 |
|---|
| 38 | EE | Leilei Song,
Keshab K. Parhi:
Efficient Finite Field Serial/Parallel Multiplication.
ASAP 1996: 72- |
| 37 | EE | David A. Parker,
Keshab K. Parhi:
Area-Efficient Parallel FIR Digital Filter Implementations.
ASAP 1996: 93-111 |
| 36 | EE | Janardhan H. Satyanarayana,
Keshab K. Parhi:
HEAT: Hierarchical Energy Analysis Tool.
DAC 1996: 9-14 |
| 35 | EE | Yun-Nan Chang,
Ching-Yi Wang,
Keshab K. Parhi:
Loop-List Scheduling for Heterogeneous Functional Units.
Great Lakes Symposium on VLSI 1996: 2-7 |
| 34 | EE | Janardhan H. Satyanarayana,
Keshab K. Parhi,
Leilei Song,
Yun-Nan Chang:
Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.
ICCD 1996: 492-499 |
| 33 | EE | Tracy C. Denk,
Keshab K. Parhi:
Lower bounds on memory requirements for statically scheduled DSP programs.
VLSI Signal Processing 12(3): 247-264 (1996) |
| 1995 |
|---|
| 32 | EE | Hosahalli R. Srinivas,
Keshab K. Parhi:
A floating point radix 2 shared division/square root chip.
ICCD 1995: 472-478 |
| 31 | | Bin Fu,
Keshab K. Parhi:
Two VLSI Design Advances in Arithmetic Coding.
ISCAS 1995: 1440-1443 |
| 30 | | Darren N. Pearson,
Keshab K. Parhi:
Low-Power FIR Digital Filter Architectures.
ISCAS 1995: 231-234 |
| 29 | | Bin Fu,
Keshab K. Parhi:
Generalized Multiplication Free Arithmetic Codes.
ISCAS 1995: 437-440 |
| 28 | | Jin-Gyun Chung,
Keshab K. Parhi:
Synthesis and Pipelining of Ladder Wave Digital Filters in Digital Domain.
ISCAS 1995: 77-80 |
| 27 | EE | W. Amendola Jr.,
Hosahalli R. Srinivas,
Keshab K. Parhi:
A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging.
VLSI Design 1995: 398-402 |
| 26 | | Hosahalli R. Srinivas,
Keshab K. Parhi:
A Fast Radix-4 Division Algorithm and Its Architecture.
IEEE Trans. Computers 44(6): 826-831 (1995) |
| 25 | EE | Ching-Yi Wang,
Keshab K. Parhi:
High-level DSP synthesis using concurrent transformations, scheduling, and allocation.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 274-295 (1995) |
| 24 | EE | Ching-Yi Wang,
Keshab K. Parhi:
Resource-constrained loop list scheduler for DSP algorithms.
VLSI Signal Processing 11(1-2): 75-96 (1995) |
| 23 | EE | Kazuhito Ito,
Keshab K. Parhi:
Determining the minimum iteration period of an algorithm.
VLSI Signal Processing 11(3): 229-244 (1995) |
| 22 | EE | Keshab K. Parhi:
High-level algorithm and architecture transformations for DSP synthesis.
VLSI Signal Processing 9(1-2): 121-143 (1995) |
| 1994 |
|---|
| 21 | EE | Kazuhito Ito,
Lori E. Lucke,
Keshab K. Parhi:
Module selection and data format conversion for cost-optimal DSP synthesis.
ICCAD 1994: 322-329 |
| 20 | | Hosahalli R. Srinivas,
Keshab K. Parhi:
A Fast Radix-4 Division Algorithm.
ISCAS 1994: 311-314 |
| 19 | | Tracy C. Denk,
Keshab K. Parhi:
Calculation of Minimum Number of Registers in 2-D Discrete Wavelet Transforms Using Lapped Block Processing.
ISCAS 1994: 77-80 |
| 18 | | Keshab K. Parhi:
Calculation of Minimum Number of Registers in Arbitrary Life Time Chart.
VLSI Design 1994: 83-86 |
| 17 | | Keshab K. Parhi,
Frank H. Wu,
Kalyan Genesan:
Sequential and Parallel Neural Network Vector Quantizers.
IEEE Trans. Computers 43(1): 104-109 (1994) |
| 16 | EE | Hosahalli R. Srinivas,
Bapiraju Vinnakota,
Keshab K. Parhi:
A C-testable carry-free divider.
IEEE Trans. VLSI Syst. 2(4): 472-488 (1994) |
| 1993 |
|---|
| 15 | | Hosahalli R. Srinivas,
Bapiraju Vinnakota,
Keshab K. Parhi:
A C-Testable Carry-Free Divider.
ICCD 1993: 206-213 |
| 14 | | Ching-Yi Wang,
Keshab K. Parhi:
Loop List Scheduler for DSP Algorithms under Resource Consraints.
ISCAS 1993: 1662-1665 |
| 13 | | Keshab K. Parhi,
Takao Nishitani:
Folded VLSI Architectures for Discrete Wavelet Transforms.
ISCAS 1993: 1734-1737 |
| 12 | | Naresh R. Shanbhag,
Keshab K. Parhi:
A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications.
ISCAS 1993: 1956-1958 |
| 11 | | Kalavai J. Raghunath,
Keshab K. Parhi:
High Speed RLS Using Scaled Tangent Rotations (STAR).
ISCAS 1993: 1959-1962 |
| 10 | | Jin-Gyun Chung,
Keshab K. Parhi:
The scaled normalized lattice digital filter.
ISCAS 1993: 483-486 |
| 9 | | Naresh R. Shanbhag,
Keshab K. Parhi:
Roundoff error analysis of the pipelined ADPCM coder.
ISCAS 1993: 886-889 |
| 8 | | Gireesh Shrimali,
Keshab K. Parhi:
High-Speed Arithmetic Coder/Decoder Architectures.
PPSC 1993: 1025-1032 |
| 7 | EE | Keshab K. Parhi,
Takao Nishitani:
VLSI architectures for discrete wavelet transforms.
IEEE Trans. VLSI Syst. 1(2): 191-202 (1993) |
| 6 | EE | Lori E. Lucke,
Keshab K. Parhi:
Data-flow transformations for critical path time reduction in high-level DSP synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1063-1068 (1993) |
| 1992 |
|---|
| 5 | EE | Hosahalli R. Srinivas,
Keshab K. Parhi:
High-speed VLSI arithmetic processor architectures using hybrid number representation.
VLSI Signal Processing 4(2-3): 177-198 (1992) |
| 1991 |
|---|
| 4 | | Hosahalli R. Srinivas,
Keshab K. Parhi:
High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation.
ICCD 1991: 564-571 |
| 3 | | Keshab K. Parhi,
David G. Messerschmitt:
Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding.
IEEE Trans. Computers 40(2): 178-195 (1991) |
| 1989 |
|---|
| 2 | | Keshab K. Parhi,
David G. Messerschmitt:
Fully-Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding.
ICPP (1) 1989: 209-216 |
| 1 | | Rajiv Ramaswami,
Keshab K. Parhi:
Distributed Scheduling of Broadcasts in a Radio Network.
INFOCOM 1989: 497-504 |
