Yasuaki Inoue

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33EEShin-ichi Ohkawa, Hiroo Masuda, Yasuaki Inoue: A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design. IEICE Transactions 91-A(4): 1062-1070 (2008)
32EEShuaiqi Wang, Fule Li, Yasuaki Inoue: A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique. IEICE Transactions 91-A(9): 2465-2474 (2008)
31EEZhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue: Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies. ASP-DAC 2007: 565-570
30EEJun Pan, Yasuaki Inoue, Zheng Liang: An Energy Management Circuit for Self-Powered Ubiquitous Sensor Modules Using Vibration-Based Energy. IEICE Transactions 90-A(10): 2116-2123 (2007)
29EEHong Yu, Yasuaki Inoue, Kazutoshi Sako, Xiaochuan Hu, Zhangcai Huang: An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm. IEICE Transactions 90-A(10): 2124-2131 (2007)
28EEZhangcai Huang, Yasuaki Inoue, Hong Yu, Jun Pan, Yun Yang, Quan Zhang, Shuai Fang: Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System. IEICE Transactions 90-A(4): 732-740 (2007)
27EEJun Pan, Yasuaki Inoue, Zheng Liang, Zhangcai Huang, Weilun Huang: A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect. IEICE Transactions 90-A(4): 748-755 (2007)
26EEZhangcai Huang, Yasuaki Inoue, Hong Yu, Quan Zhang: A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback. APCCAS 2006: 708-711
25EEHong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang: An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits. ISCAS 2006
24EEZhangcai Huang, Yasuaki Inoue, Quan Zhang, Yuehu Zhou, Long Xie, Harutoshi Ogai: Behavioral macromodeling of analog LSI implementation for automobile intake system. ISCAS 2006
23EEHong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang: An Effective Pseudo-Transient Algorithm for Finding Dc Solutions of Nonlinear Circuits. IEICE Transactions 89-A(10): 2724-2731 (2006)
22EEShuaiqi Wang, Fule Li, Yasuaki Inoue: A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle. IEICE Transactions 89-A(10): 2732-2739 (2006)
21EEZhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue: Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay. IEICE Transactions 89-A(4): 840-846 (2006)
20EEAtsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda: Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills. IEICE Transactions 89-A(4): 847-855 (2006)
19EEAtsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue: Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays. IEICE Transactions 89-A(4): 856-864 (2006)
18EEYun Yang, Wenqing Zhao, Yasuaki Inoue: High-performance systolic arrays for band matrix multiplication. ISCAS (2) 2005: 1130-1133
17EEZhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue: Effective capacitance for gate delay with RC loads. ISCAS (3) 2005: 2795-2798
16EEYu Imai, Kiyotaka Yamamura, Yasuaki Inoue: An efficient homotopy method for finding DC operating points of nonlinear circuits. ISCAS (5) 2005: 4911-4914
15EEAtsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. ISQED 2005: 153-158
14EEAtsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. ISQED 2005: 586-591
13EEYu Imai, Kiyotaka Yamamura, Yasuaki Inoue: An Efficient Homotopy Method for Finding DC Operating Points of Nonlinear Circuits. IEICE Transactions 88-A(10): 2554-2561 (2005)
12EEZhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao: A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads. IEICE Transactions 88-A(10): 2562-2569 (2005)
11EEAtsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda: A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills. IEICE Transactions 88-A(11): 3180-3187 (2005)
10EEZhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue: Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew. IEICE Transactions 88-A(12): 3367-3374 (2005)
9EEYun Yang, Atsushi Kurokawa, Yasuaki Inoue, Wenqing Zhao: Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm. IEICE Transactions 88-A(12): 3412-3420 (2005)
8EEAtsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda: Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Transactions 88-A(12): 3453-3462 (2005)
7EEAtsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills. IEICE Transactions 88-A(12): 3471-3478 (2005)
6EEKiyotaka Yamamura, Wataru Kuroki, Hideaki Okuma, Yasuaki Inoue: Path Following Circuits - SPICE-Oriented Numerical Methods Where Formulas are Described by Circuits - . IEICE Transactions 88-A(4): 825-831 (2005)
5EEYasuaki Inoue, Yu Imai, Kiyotaka Yamamura: A Homotopy Method Using a Nonlinear Auxiliary Function for Solving Transistor Circuits. IEICE Transactions 88-D(7): 1401-1408 (2005)
4EEKiyotaka Yamamura, Naoya Igarashi, Yasuaki Inoue: An interval algorithm for finding all solutions of nonlinear resistive circuits. ISCAS (3) 2003: 192-195
3EEYasuaki Inoue, Saeko Kusanobu, Kiyotaka Yamamura, M. Ando: An effective initial solution algorithm for globally convergent homotopy methods. ISCAS (3) 2003: 196-199
2EEAkio Ushida, Yoshihiro Yamagami, Yoshifumi Nishio, Ikkei Kinouchi, Yasuaki Inoue: An efficient algorithm for finding multiple DC solutions based onthe SPICE-oriented Newton homotopy method. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 337-348 (2002)
1EEAkio Ushida, Yoshihiro Yamagami, Ikkei Kinouchi, Yoshifumi Nishio, Yasuaki Inoue: An efficient algorithm for finding multiple DC solutions based on Spice oriented Newton homotopy method. ISCAS (5) 2001: 447-450

Coauthor Index

1M. Ando [3]
2Wei Fong Chang [7] [14]
3Shuai Fang [28]
4Junko Fujii [19]
5Masanori Hashimoto [8]
6Xiaochuan Hu [29]
7Weilun Huang [27]
8Zhangcai Huang [8] [10] [12] [17] [19] [20] [21] [23] [24] [25] [26] [27] [28] [29] [31]
9Tetsuya Ibe [7] [14]
10Naoya Igarashi [4]
11Yu Imai [5] [13] [16]
12Ryosuke Inagaki [8]
13Toshinori Inoshita [19]
14Tetsuro Kage [7] [14] [15]
15Toshiki Kanamoto [7] [11] [14] [20]
16Akira Kasebe [7] [8] [11] [14] [19] [20]
17Ikkei Kinouchi [1] [2]
18Atsushi Kurokawa [7] [8] [9] [10] [11] [12] [14] [15] [17] [19] [20] [21] [31]
19Wataru Kuroki [6]
20Saeko Kusanobu [3]
21Fule Li [22] [32]
22Zheng Liang [27] [30]
23Junfa Mao [12]
24Hiroo Masuda [7] [8] [11] [14] [15] [19] [20] [33]
25Yuki Matsuya [23] [25]
26Yoshifumi Nishio [1] [2]
27Harutoshi Ogai [24]
28Shin-ichi Ohkawa [33]
29Hideaki Okuma [6]
30Nobuto Ono [15]
31Jun Pan [10] [27] [28] [30]
32Kazutoshi Sako [29]
33Akio Ushida [1] [2]
34Shuaiqi Wang [22] [32]
35Long Xie [24]
36Yoshihiro Yamagami [1] [2]
37Masaharu Yamamoto [15]
38Kiyotaka Yamamura [3] [4] [5] [6] [13] [16]
39Yun Yang [8] [9] [18] [20] [21] [28]
40Hong Yu [21] [23] [25] [26] [28] [29] [31]
41Quan Zhang [24] [26] [28]
42Wenqing Zhao [9] [18]
43Yuehu Zhou [24]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)