Yasuaki Inoue

2008
33	EE	Shin-ichi Ohkawa, Hiroo Masuda, Yasuaki Inoue: A Novel Expression of Spatial Correlation by a Random Curved Surface Model and Its Application to LSI Design. IEICE Transactions 91-A(4): 1062-1070 (2008)
32	EE	Shuaiqi Wang, Fule Li, Yasuaki Inoue: A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique. IEICE Transactions 91-A(9): 2465-2474 (2008)
2007
31	EE	Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue: Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies. ASP-DAC 2007: 565-570
30	EE	Jun Pan, Yasuaki Inoue, Zheng Liang: An Energy Management Circuit for Self-Powered Ubiquitous Sensor Modules Using Vibration-Based Energy. IEICE Transactions 90-A(10): 2116-2123 (2007)
29	EE	Hong Yu, Yasuaki Inoue, Kazutoshi Sako, Xiaochuan Hu, Zhangcai Huang: An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm. IEICE Transactions 90-A(10): 2124-2131 (2007)
28	EE	Zhangcai Huang, Yasuaki Inoue, Hong Yu, Jun Pan, Yun Yang, Quan Zhang, Shuai Fang: Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System. IEICE Transactions 90-A(4): 732-740 (2007)
27	EE	Jun Pan, Yasuaki Inoue, Zheng Liang, Zhangcai Huang, Weilun Huang: A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect. IEICE Transactions 90-A(4): 748-755 (2007)
2006
26	EE	Zhangcai Huang, Yasuaki Inoue, Hong Yu, Quan Zhang: A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback. APCCAS 2006: 708-711
25	EE	Hong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang: An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits. ISCAS 2006
24	EE	Zhangcai Huang, Yasuaki Inoue, Quan Zhang, Yuehu Zhou, Long Xie, Harutoshi Ogai: Behavioral macromodeling of analog LSI implementation for automobile intake system. ISCAS 2006
23	EE	Hong Yu, Yasuaki Inoue, Yuki Matsuya, Zhangcai Huang: An Effective Pseudo-Transient Algorithm for Finding Dc Solutions of Nonlinear Circuits. IEICE Transactions 89-A(10): 2724-2731 (2006)
22	EE	Shuaiqi Wang, Fule Li, Yasuaki Inoue: A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle. IEICE Transactions 89-A(10): 2732-2739 (2006)
21	EE	Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue: Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay. IEICE Transactions 89-A(4): 840-846 (2006)
20	EE	Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda: Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills. IEICE Transactions 89-A(4): 847-855 (2006)
19	EE	Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue: Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays. IEICE Transactions 89-A(4): 856-864 (2006)
2005
18	EE	Yun Yang, Wenqing Zhao, Yasuaki Inoue: High-performance systolic arrays for band matrix multiplication. ISCAS (2) 2005: 1130-1133
17	EE	Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue: Effective capacitance for gate delay with RC loads. ISCAS (3) 2005: 2795-2798
16	EE	Yu Imai, Kiyotaka Yamamura, Yasuaki Inoue: An efficient homotopy method for finding DC operating points of nonlinear circuits. ISCAS (5) 2005: 4911-4914
15	EE	Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. ISQED 2005: 153-158
14	EE	Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. ISQED 2005: 586-591
13	EE	Yu Imai, Kiyotaka Yamamura, Yasuaki Inoue: An Efficient Homotopy Method for Finding DC Operating Points of Nonlinear Circuits. IEICE Transactions 88-A(10): 2554-2561 (2005)
12	EE	Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao: A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads. IEICE Transactions 88-A(10): 2562-2569 (2005)
11	EE	Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda: A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills. IEICE Transactions 88-A(11): 3180-3187 (2005)
10	EE	Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue: Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew. IEICE Transactions 88-A(12): 3367-3374 (2005)
9	EE	Yun Yang, Atsushi Kurokawa, Yasuaki Inoue, Wenqing Zhao: Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm. IEICE Transactions 88-A(12): 3412-3420 (2005)
8	EE	Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda: Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Transactions 88-A(12): 3453-3462 (2005)
7	EE	Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda: Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills. IEICE Transactions 88-A(12): 3471-3478 (2005)
6	EE	Kiyotaka Yamamura, Wataru Kuroki, Hideaki Okuma, Yasuaki Inoue: Path Following Circuits - SPICE-Oriented Numerical Methods Where Formulas are Described by Circuits - . IEICE Transactions 88-A(4): 825-831 (2005)
5	EE	Yasuaki Inoue, Yu Imai, Kiyotaka Yamamura: A Homotopy Method Using a Nonlinear Auxiliary Function for Solving Transistor Circuits. IEICE Transactions 88-D(7): 1401-1408 (2005)
2003
4	EE	Kiyotaka Yamamura, Naoya Igarashi, Yasuaki Inoue: An interval algorithm for finding all solutions of nonlinear resistive circuits. ISCAS (3) 2003: 192-195
3	EE	Yasuaki Inoue, Saeko Kusanobu, Kiyotaka Yamamura, M. Ando: An effective initial solution algorithm for globally convergent homotopy methods. ISCAS (3) 2003: 196-199
2002
2	EE	Akio Ushida, Yoshihiro Yamagami, Yoshifumi Nishio, Ikkei Kinouchi, Yasuaki Inoue: An efficient algorithm for finding multiple DC solutions based onthe SPICE-oriented Newton homotopy method. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 337-348 (2002)
2001
1	EE	Akio Ushida, Yoshihiro Yamagami, Ikkei Kinouchi, Yoshifumi Nishio, Yasuaki Inoue: An efficient algorithm for finding multiple DC solutions based on Spice oriented Newton homotopy method. ISCAS (5) 2001: 447-450

Coauthor Index

1	M. Ando	[3]
2	Wei Fong Chang	[7] [14]
3	Shuai Fang	[28]
4	Junko Fujii	[19]
5	Masanori Hashimoto	[8]
6	Xiaochuan Hu	[29]
7	Weilun Huang	[27]
8	Zhangcai Huang	[8] [10] [12] [17] [19] [20] [21] [23] [24] [25] [26] [27] [28] [29] [31]
9	Tetsuya Ibe	[7] [14]
10	Naoya Igarashi	[4]
11	Yu Imai	[5] [13] [16]
12	Ryosuke Inagaki	[8]
13	Toshinori Inoshita	[19]
14	Tetsuro Kage	[7] [14] [15]
15	Toshiki Kanamoto	[7] [11] [14] [20]
16	Akira Kasebe	[7] [8] [11] [14] [19] [20]
17	Ikkei Kinouchi	[1] [2]
18	Atsushi Kurokawa	[7] [8] [9] [10] [11] [12] [14] [15] [17] [19] [20] [21] [31]
19	Wataru Kuroki	[6]
20	Saeko Kusanobu	[3]
21	Fule Li	[22] [32]
22	Zheng Liang	[27] [30]
23	Junfa Mao	[12]
24	Hiroo Masuda	[7] [8] [11] [14] [15] [19] [20] [33]
25	Yuki Matsuya	[23] [25]
26	Yoshifumi Nishio	[1] [2]
27	Harutoshi Ogai	[24]
28	Shin-ichi Ohkawa	[33]
29	Hideaki Okuma	[6]
30	Nobuto Ono	[15]
31	Jun Pan	[10] [27] [28] [30]
32	Kazutoshi Sako	[29]
33	Akio Ushida	[1] [2]
34	Shuaiqi Wang	[22] [32]
35	Long Xie	[24]
36	Yoshihiro Yamagami	[1] [2]
37	Masaharu Yamamoto	[15]
38	Kiyotaka Yamamura	[3] [4] [5] [6] [13] [16]
39	Yun Yang	[8] [9] [18] [20] [21] [28]
40	Hong Yu	[21] [23] [25] [26] [28] [29] [31]
41	Quan Zhang	[24] [26] [28]
42	Wenqing Zhao	[9] [18]
43	Yuehu Zhou	[24]

Colors in the list of coauthors