| 2003 |
|---|
| 9 | EE | Takahisa Hiraide,
Kwame Osei Boateng,
Hideaki Konishi,
Koichi Itaya,
Michiaki Emori,
Hitoshi Yamanaka,
Takashi Mochiyama:
BIST-Aided Scan Test - A New Method for Test Cost Reduction.
VTS 2003: 359-364 |
| 2002 |
|---|
| 8 | EE | Hiroshi Takahashi,
Kwame Osei Boateng,
Kewal K. Saluja,
Yuzo Takamatsu:
On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 362-368 (2002) |
| 2001 |
|---|
| 7 | EE | Kwame Osei Boateng,
Hideaki Konishi,
Tsuneo Nakata:
A Method of Static Compaction of Test Stimuli.
Asian Test Symposium 2001: 137-144 |
| 2000 |
|---|
| 6 | EE | Kwame Osei Boateng,
Hiroshi Takahashi,
Yuzo Takamatsu:
General BIST-Amenable Method of Test Generation for Iterative Logic Arrays.
VTS 2000: 171-178 |
| 1999 |
|---|
| 5 | EE | Hiroshi Takahashi,
Kwame Osei Boateng,
Yuzo Takamatsu,
Nobuhiro Yanagida:
Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators.
Asian Test Symposium 1999: 341-346 |
| 4 | EE | Hiroshi Takahashi,
Kwame Osei Boateng,
Yuzo Takamatsu:
A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations.
VTS 1999: 64-69 |
| 1998 |
|---|
| 3 | EE | Hiroshi Takahashi,
Kwame Osei Boateng,
Yuzo Takamatsu:
Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation.
Asian Test Symposium 1998: 108-112 |
| 1997 |
|---|
| 2 | EE | Hiroshi Takahashi,
Kwame Osei Boateng,
Yuzo Takamatsu,
Toshiyuki Matsunaga:
A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits.
Asian Test Symposium 1997: 320-325 |
| 1 | EE | Kwame Osei Boateng,
Hiroshi Takahashi,
Yuzo Takamatsu:
Design of C-Testable Multipliers Based on the Modified Booth Algorithm.
Asian Test Symposium 1997: 42-47 |
