Yih-Chih Chou

List of publications from the DBLP Bibliography Server - FAQ

2002

5 EE Yih-Chih Chou, Youn-Long Lin: Effective enforcement of path-delay constraints inperformance-driven placement. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 15-22 (2002)

2001

4 EE Yih-Chih Chou, Youn-Long Lin: A 3-step approach for performance-driven whole-chip routing. ASP-DAC 2001: 187-191

3 EE Yih-Chih Chou, Youn-Long Lin: A performance-driven standard-cell placer based on a modified force-directed algorithm. ISPD 2001: 24-29

1998

2 EE Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin: Integrating logic retiming and register placement. ICCAD 1998: 136-139

1 EE Yih-Chih Chou, Youn-Long Lin: A graph-partitioning-based approach for multi-layer constrained via minimization. ICCAD 1998: 426-429

2002
5	EE	Yih-Chih Chou, Youn-Long Lin: Effective enforcement of path-delay constraints inperformance-driven placement. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 15-22 (2002)
2001
4	EE	Yih-Chih Chou, Youn-Long Lin: A 3-step approach for performance-driven whole-chip routing. ASP-DAC 2001: 187-191
3	EE	Yih-Chih Chou, Youn-Long Lin: A performance-driven standard-cell placer based on a modified force-directed algorithm. ISPD 2001: 24-29
1998
2	EE	Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin: Integrating logic retiming and register placement. ICCAD 1998: 136-139
1	EE	Yih-Chih Chou, Youn-Long Lin: A graph-partitioning-based approach for multi-layer constrained via minimization. ICCAD 1998: 426-429

Coauthor Index