| 2002 |
|---|
| 6 | EE | Padmini Gopalakrishnan,
Altan Odabasioglu,
Lawrence T. Pileggi,
Salil Raje:
An analysis of the wire-load model uncertainty problem.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 23-31 (2002) |
| 2001 |
|---|
| 5 | EE | Padmini Gopalakrishnan,
Altan Odabasioglu,
Lawrence T. Pileggi,
Salil Raje:
Overcoming wireload model uncertainty during physical design.
ISPD 2001: 182-189 |
| 1999 |
|---|
| 4 | EE | Emrah Acar,
Altan Odabasioglu,
Mustafa Celik,
Lawrence T. Pileggi:
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric.
Great Lakes Symposium on VLSI 1999: 60-63 |
| 3 | EE | Altan Odabasioglu,
Mustafa Celik,
Lawrence T. Pileggi:
Practical considerations for passive reduction of RLC circuits.
ICCAD 1999: 214-220 |
| 1998 |
|---|
| 2 | EE | Altan Odabasioglu,
Mustafa Celik,
Lawrence T. Pileggi:
PRIMA: passive reduced-order interconnect macromodeling algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 645-654 (1998) |
| 1997 |
|---|
| 1 | EE | Altan Odabasioglu,
Mustafa Celik,
Lawrence T. Pileggi:
PRIMA: passive reduced-order interconnect macromodeling algorithm.
ICCAD 1997: 58-65 |
