2004 |
17 | EE | Navaratnasothie Selvakkumaran,
Abhishek Ranjan,
Salil Raje,
George Karypis:
Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources.
DAC 2004: 741-746 |
16 | EE | André DeHon,
Brad L. Hutchings,
Daryl Rudusky,
James Hwang,
Nikhil,
Salil Raje,
Adrian Stoica:
What is the right model for programming and using modern FPGAs?
FPGA 2004: 119 |
15 | EE | Navaratnasothie Selvakkumaran,
Abhishek Ranjan,
Salil Raje,
George Karypis:
Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources.
FPGA 2004: 253 |
14 | EE | Taraneh Taghavi,
Soheil Ghiasi,
Abhishek Ranjan,
Salil Raje,
Majid Sarrafzadeh:
Innovate or perish: FPGA physical design.
ISPD 2004: 148-155 |
2003 |
13 | EE | Maogang Wang,
Abhishek Ranjan,
Salil Raje:
Multi-Million Gate FPGA Physical Design Challenges.
ICCAD 2003: 891-899 |
2002 |
12 | EE | Padmini Gopalakrishnan,
Altan Odabasioglu,
Lawrence T. Pileggi,
Salil Raje:
An analysis of the wire-load model uncertainty problem.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 23-31 (2002) |
2001 |
11 | EE | Padmini Gopalakrishnan,
Altan Odabasioglu,
Lawrence T. Pileggi,
Salil Raje:
Overcoming wireload model uncertainty during physical design.
ISPD 2001: 182-189 |
1999 |
10 | EE | Majid Sarrafzadeh,
Salil Raje:
Scheduling with multiple voltages under resource constraints.
ISCAS (1) 1999: 350-353 |
1998 |
9 | | Jun Dong Cho,
Salil Raje,
Majid Sarrafzadeh:
Fast Approximation Algorithms on Maxcut, k-Coloring, and k-Color Ordering vor VLSI Applications.
IEEE Trans. Computers 47(11): 1253-1266 (1998) |
1997 |
8 | EE | Salil Raje,
Reinaldo A. Bergamaschi:
Generalized resource sharing.
ICCAD 1997: 326-332 |
7 | EE | Reinaldo A. Bergamaschi,
Salil Raje:
Observable Time Windows: Verifying High-Level Synthesis Results.
IEEE Design & Test of Computers 14(2): 40-50 (1997) |
6 | EE | Reinaldo A. Bergamaschi,
Salil Raje,
Indira Nair,
Louise Trevillyan:
Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system.
IEEE Trans. VLSI Syst. 5(1): 82-100 (1997) |
5 | EE | Salil Raje,
Majid Sarrafzadeh:
Scheduling with multiple voltages.
Integration 23(1): 37-59 (1997) |
1995 |
4 | EE | Elof Frank,
Salil Raje,
Majid Sarrafzadeh:
Constrained Register Allocation in Bus Architectures.
DAC 1995: 170-175 |
3 | EE | Salil Raje,
Majid Sarrafzadeh:
Variable voltage scheduling.
ISLPD 1995: 9-14 |
1994 |
2 | | Jun Dong Cho,
Salil Raje,
Majid Sarrafzadeh:
Approximation Algorithm on Multi-Way Maxcut Partitioning.
ESA 1994: 148-158 |
1993 |
1 | | Salil Raje,
Majid Sarrafzadeh:
GEM: A Geometric Algorithm for Scheduling.
ISCAS 1993: 1991-1994 |