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Salil Raje

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2004
17EENavaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis: Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources. DAC 2004: 741-746
16EEAndré DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica: What is the right model for programming and using modern FPGAs? FPGA 2004: 119
15EENavaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis: Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources. FPGA 2004: 253
14EETaraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh: Innovate or perish: FPGA physical design. ISPD 2004: 148-155
2003
13EEMaogang Wang, Abhishek Ranjan, Salil Raje: Multi-Million Gate FPGA Physical Design Challenges. ICCAD 2003: 891-899
2002
12EEPadmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje: An analysis of the wire-load model uncertainty problem. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 23-31 (2002)
2001
11EEPadmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje: Overcoming wireload model uncertainty during physical design. ISPD 2001: 182-189
1999
10EEMajid Sarrafzadeh, Salil Raje: Scheduling with multiple voltages under resource constraints. ISCAS (1) 1999: 350-353
1998
9 Jun Dong Cho, Salil Raje, Majid Sarrafzadeh: Fast Approximation Algorithms on Maxcut, k-Coloring, and k-Color Ordering vor VLSI Applications. IEEE Trans. Computers 47(11): 1253-1266 (1998)
1997
8EESalil Raje, Reinaldo A. Bergamaschi: Generalized resource sharing. ICCAD 1997: 326-332
7EEReinaldo A. Bergamaschi, Salil Raje: Observable Time Windows: Verifying High-Level Synthesis Results. IEEE Design & Test of Computers 14(2): 40-50 (1997)
6EEReinaldo A. Bergamaschi, Salil Raje, Indira Nair, Louise Trevillyan: Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system. IEEE Trans. VLSI Syst. 5(1): 82-100 (1997)
5EESalil Raje, Majid Sarrafzadeh: Scheduling with multiple voltages. Integration 23(1): 37-59 (1997)
1995
4EEElof Frank, Salil Raje, Majid Sarrafzadeh: Constrained Register Allocation in Bus Architectures. DAC 1995: 170-175
3EESalil Raje, Majid Sarrafzadeh: Variable voltage scheduling. ISLPD 1995: 9-14
1994
2 Jun Dong Cho, Salil Raje, Majid Sarrafzadeh: Approximation Algorithm on Multi-Way Maxcut Partitioning. ESA 1994: 148-158
1993
1 Salil Raje, Majid Sarrafzadeh: GEM: A Geometric Algorithm for Scheduling. ISCAS 1993: 1991-1994

Coauthor Index

1Reinaldo A. Bergamaschi [6] [7] [8]
2Jun Dong Cho [2] [9]
3André DeHon [16]
4Elof Frank [4]
5Soheil Ghiasi [14]
6Padmini Gopalakrishnan [11] [12]
7Brad L. Hutchings [16]
8James Hwang [16]
9George Karypis [15] [17]
10Indira Nair [6]
11 Nikhil [16]
12Altan Odabasioglu [11] [12]
13Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage) [11] [12]
14Abhishek Ranjan [13] [14] [15] [17]
15Daryl Rudusky [16]
16Majid Sarrafzadeh [1] [2] [3] [4] [5] [9] [10] [14]
17Navaratnasothie Selvakkumaran [15] [17]
18Adrian Stoica [16]
19Taraneh Taghavi [14]
20Louise Trevillyan [6]
21Maogang Wang [13]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)