2008 | ||
---|---|---|
45 | EE | Sukanta Das, Chandrama Shaw, Biplab K. Sikdar: Exploring CAState Space to Synthesize Cellular Automata with Specified Attractor Set. ACRI 2008: 152-159 |
44 | EE | Sukanta Das, Biplab K. Sikdar: Characterization of Non-reachable States in Irreversible CAState Space. ACRI 2008: 160-167 |
43 | EE | Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri: Exploring Cycle Structures of Additive Cellular Automata. Fundam. Inform. 87(2): 137-154 (2008) |
42 | EE | Debashis Moitra, Sandip Dhar, J. M. Mallick, S. Sadhu, Biplab K. Sikdar: Cellular Automata Based Design of Cost Optimal Steel Building Frames. Fundam. Inform. 87(2): 227-245 (2008) |
2007 | ||
41 | Sukanta Das, Sipra DasBit, Biplab K. Sikdar: CA Based Data Servicing In Cellular Mobile Network. ICWN 2007: 280-286 | |
40 | Debashis Moitra, Sandip Dhar, J. M. Mallick, Biplab K. Sikdar: Cellular Automata Model for Cost Optimal Design of Steel Building Frames. IICAI 2007: 1440-1455 | |
39 | EE | Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan: Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). VTS 2007: 422-430 |
2006 | ||
38 | EE | Chandrama Shaw, Sukanta Das, Biplab K. Sikdar: Cellular Automata Based Encoding Technique for Wavelet Transformed Data Targeting Still Image Compression. ACRI 2006: 141-146 |
37 | EE | Sukanta Das, Biplab K. Sikdar: Classification of CA Rules Targeting Synthesis of Reversible Cellular Automata. ACRI 2006: 68-77 |
2005 | ||
36 | EE | Sukanta Das, Hafizur Rahaman, Biplab K. Sikdar: Cost Optimal Design of Nonlinear CA based PRPG for Test Applications. Asian Test Symposium 2005: 284-287 |
35 | EE | Biplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das: Synthesis of Testable Finite State Machine Through Decomposition. Asian Test Symposium 2005: 398-403 |
34 | EE | Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das: Cellular Automata Based Test Structures with Logic Folding. VLSI Design 2005: 71-74 |
33 | EE | Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri: Fault diagnosis of VLSI circuits with cellular automata based pattern classifier. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1115-1131 (2005) |
32 | EE | Biplab K. Sikdar, Samir Roy, Debesh K. Das: A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. J. Electronic Testing 21(1): 83-93 (2005) |
31 | EE | Sukanta Das, Anirban Kundu, Biplab K. Sikdar, Parimal Pal Chaudhuri: Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time. J. Electronic Testing 21(1): 95-107 (2005) |
2004 | ||
30 | EE | Chandrama Shaw, Pradipta Maji, Sourav Saha, Biplab K. Sikdar, Samir Roy, Parimal Pal Chaudhuri: Cellular Automata Based Encompression Technology for Voice Data. ACRI 2004: 258-267 |
29 | EE | Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri: Cellular Automata Evolution for Distributed Data Mining. ACRI 2004: 40-49 |
28 | EE | Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri: Cellular Automata Evolution for Pattern Classification. ACRI 2004: 660-669 |
27 | EE | Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri: Characterization of Reachable/Nonreachable Cellular Automata States. ACRI 2004: 813-822 |
26 | EE | Sukanta Das, Debdas Dey, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri: An efficient design of non-linear CA based PRPG for VLSI circuit testing. ASP-DAC 2004: 110-112 |
25 | EE | Sukanta Das, Anirban Kundu, Biplab K. Sikdar: Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant Faults. Asian Test Symposium 2004: 196-201 |
24 | EE | Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri: Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores. Asian Test Symposium 2004: 331-334 |
23 | EE | Chandrama Shaw, Biplab K. Sikdar, N. C. Maiti: CA Based Document Compression Technology. ICONIP 2004: 679-685 |
22 | EE | Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri: Generation of test patterns without prohibited pattern set. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1650-1660 (2004) |
2003 | ||
21 | EE | Samir Roy, Biplab K. Sikdar: Power Conscious BIST Design for Sequential Circuits Using ghost-FSM. Asian Test Symposium 2003: 190-195 |
20 | EE | Sukanta Das, Anirban Kundu, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri: Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity. Asian Test Symposium 2003: 78-83 |
19 | EE | Samir Roy, U. Maulik, Biplab K. Sikdar: Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines. VLSI Design 2003: 155-160 |
18 | EE | Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri: Design Of A Universal BIST (UBIST) Structure. VLSI Design 2003: 161-166 |
17 | EE | Pradipta Maji, Chandrama Shaw, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri: Theory and Application of Cellular Automata For Pattern Classification. Fundam. Inform. 58(2003): 321-354 (2003) |
2002 | ||
16 | EE | Niloy Ganguly, Pradipta Maji, Sandip Dhar, Biplab K. Sikdar, Parimal Pal Chaudhuri: Evolving Cellular Automata as Pattern Classifier. ACRI 2002: 56-68 |
15 | EE | Niloy Ganguly, Pradipta Maji, Arijit Das, Biplab K. Sikdar, Parimal Pal Chaudhuri: Characterization of Non-linear Cellular Automata Model for Pattern Recognition. AFSS 2002: 214-220 |
14 | EE | Niloy Ganguly, Anindyasundar Nandi, Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri: An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). Asian Test Symposium 2002: 260-265 |
13 | EE | Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das: Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. VLSI Design 2002: 671-676 |
12 | EE | Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri: Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS). VLSI Design 2002: 689- |
11 | EE | Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri: Design of hierarchical cellular automata for on-chip test pattern generator. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1530-1539 (2002) |
10 | EE | Niloy Ganguly, Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri: Generalized Multiple Attractor Cellular Automata (GMACA) Model for Associative Memory. IJPRAI 16(7): 781-796 (2002) |
2001 | ||
9 | EE | Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri: Cellular automata as a built in self test structure. ASP-DAC 2001: 319-324 |
8 | EE | Biplab K. Sikdar, Samir Roy, Debesh K. Das: Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis. Asian Test Symposium 2001: 285- |
7 | EE | Biplab K. Sikdar, Niloy Ganguly, Aniket Karmakar, Subha Sankar Chowdhury, Parimal Pal Chaudhuri: Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits. Asian Test Symposium 2001: 385-390 |
6 | EE | Niloy Ganguly, Arijit Das, Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri: Evolving Cellular Automata Based Associative Memory for Pattern Recognition. HiPC 2001: 115-124 |
5 | EE | Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly: Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. VLSI Design 2001: 403- |
4 | EE | Biplab K. Sikdar, Purnabha Majumder, Parimal Pal Chaudhuri, Niloy Ganguly: Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits. VLSI Design 2001: 454-459 |
2000 | ||
3 | EE | Kolin Paul, Ranadeep Ghosal, Biplab K. Sikdar, Santashil Pal Chaudhuri, Dipanwita Roy Chowdhury: GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images. VLSI Design 2000: 140-143 |
2 | Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar: Theory and Applications of Cellular Automata for VLSI Design and Testing. VLSI Design 2000: 4 | |
1 | EE | Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee: Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. VLSI Design 2000: 556-561 |