| |
| 2002 | ||
|---|---|---|
| 5 | EE | Cagdas Akturan, Margarida F. Jacome: RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1395-1415 (2002) |
| 2001 | ||
| 4 | EE | Cagdas Akturan, Margarida F. Jacome: RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors. CODES 2001: 67-72 |
| 3 | EE | Cagdas Akturan, Margarida F. Jacome: CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors. ICCAD 2001: 112-118 |
| 2000 | ||
| 2 | EE | Cagdas Akturan, Margarida F. Jacome: FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors. ISSS 2000: 34-40 |
| 1999 | ||
| 1 | EE | Margarida F. Jacome, Gustavo de Veciana, Cagdas Akturan: Resource constrained dataflow retiming heuristics for VLIW ASIPs. CODES 1999: 12-16 |
| 1 | Margarida F. Jacome | [1] [2] [3] [4] [5] |
| 2 | Gustavo de Veciana | [1] |