José Luis Rosselló

2008
18	EE	José Luis Rosselló, Vincent Canals, Ivan de Paúl, Jaume Segura: Using stochastic logic for efficient pattern recognition analysis. IJCNN 2008: 1057-1061
2007
17	EE	José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura: Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. DATE 2007: 1271-1276
16	EE	Sebstatià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura: Smart Temperature Sensor for Thermal Testing of Cell-Based ICs CoRR abs/0710.4733: (2007)
15	EE	José Luis Rosselló, Vicens Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura: A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs CoRR abs/0710.4759: (2007)
2006
14	EE	José Luis Rosselló, Jaume Segura: A compact model to identify delay faults due to crosstalk. DATE 2006: 902-906
13	EE	José Luis Rosselló, Sebastià A. Bota, Vicens Canals, Ivan de Paúl, Jaume Segura: A Fully CMOS Low-Cost Chaotic Neural Network. IJCNN 2006: 659-663
12	EE	José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura: Leakage Power Characterization Considering Process Variations. PATMOS 2006: 66-74
11	EE	Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura: Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. VTS 2006: 358-363
10	EE	Sebastià A. Bota, José Luis Rosselló, Carol de Benito, Ali Keshavarzi, Jaume Segura: Impact of Thermal Gradients on Clock Skew and Testing. IEEE Design & Test of Computers 23(5): 414-424 (2006)
2005
9	EE	José Luis Rosselló, Vicens Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura: A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. DATE 2005: 206-211
8	EE	Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura: Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. DATE 2005: 464-465
7	EE	José Luis Rosselló, Sebastià A. Bota, Jaume Segura: Compact Static Power Model of Complex CMOS Gates. PATMOS 2005: 348-354
2004
6	EE	José Luis Rosselló, Jaume Segura: A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. DATE 2004: 954-961
5	EE	Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi: Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. ITC 2004: 1276-1284
2003
4	EE	José Luis Rosselló, Jaume Segura: A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. PATMOS 2003: 51-59
2002
3	EE	José Luis Rosselló, Jaume Segura: A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. PATMOS 2002: 219-228
2	EE	José Luis Rosselló, Jaume Segura: Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers. IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 433-448 (2002)
2001
1	EE	José Luis Rosselló, Jaume Segura: Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. ICCAD 2001: 494-

Coauthor Index

1	Carol de Benito	[10] [12] [17]
2	Sebastià A. Bota	[5] [7] [8] [9] [10] [11] [12] [13] [15] [17]
3	Sebstatià A. Bota	[16]
4	Vicens Canals	[9] [13] [15]
5	Vincent Canals	[18]
6	Ali Keshavarzi	[5] [9] [10] [15]
7	Ivan de Paúl	[13] [18]
8	M. Rosales	[5] [8] [11] [16]
9	Jaume Segura	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]