Ken S. Stevens

2007
12	EE	Michael Kishinevsky, Sandeep K. Shukla, Ken S. Stevens: Guest Editors' Introduction: GALS Design and Validation. IEEE Design & Test of Computers 24(5): 414-416 (2007)
2006
11	EE	Ken S. Stevens, Sandeep K. Shukla, Montek Singh, Jean-Pierre Talpin: Preface. Electr. Notes Theor. Comput. Sci. 146(2): 1-3 (2006)
2003
10	EE	Ken S. Stevens, Ran Ginosar, Shai Rotem: Relative timing [asynchronous design]. IEEE Trans. VLSI Syst. 11(1): 129-140 (2003)
2002
9	EE	Peter A. Beerel, Ken S. Stevens, Hoshik Kim: Relative Timing Based Verification of Timed Circuits and Systems. ASYNC 2002: 115-
8	EE	Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev: Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 109-130 (2002)
2000
7	EE	Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri: CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. ASYNC 2000: 62-72
6	EE	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy: Fsimac: a fault simulator for asynchronous sequential circuits. Asian Test Symposium 2000: 114-119
1999
5	EE	Ken S. Stevens, Shai Rotem, Ran Ginosar: Relative Timing. ASYNC 1999: 208-218
4	EE	Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun: RAPPID: An Asynchronous Instruction Length Decoder. ASYNC 1999: 60-70
3	EE	Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken: CAD Directions for High Performance Asynchronous Circuits. DAC 1999: 116-121
2	EE	Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Ken S. Stevens: Synthesis of asynchronous control circuits with automatically generated relative timing assumptions. ICCAD 1999: 324-331
1998
1	EE	Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun: Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 80-

Coauthor Index

1	Boris Agapiev	[4]
2	Peter A. Beerel	[1] [4] [9]
3	Steven M. Burns	[2] [3] [8]
4	Parimal Pal Chaudhuri	[6] [7]
5	Wei-Chun Chou	[1]
6	Jordi Cortadella	[2] [3] [8]
7	Charles Dike	[4]
8	Ran Ginosar	[1] [3] [4] [5] [10]
9	Hoshik Kim	[9]
10	Michael Kishinevsky	[2] [3] [8] [12]
11	Rakefet Kol	[1] [4]
12	Alex Kondratyev	[8]
13	Luciano Lavagno	[8]
14	Chris J. Myers	[1] [4]
15	Rajesh Pendurkar	[7]
16	Marly Roncken	[3] [4] [6] [7]
17	Shai Rotem	[1] [3] [4] [5] [7] [10]
18	Rob Roy	[6]
19	Sandeep K. Shukla	[11] [12]
20	Montek Singh	[11]
21	Susmita Sur-Kolay	[6]
22	Jean-Pierre Talpin	[11]
23	Alexander Taubin	[8]
24	Alexandre Yakovlev	[8]
25	Kenneth Y. Yun	[1] [4]