Florentin Dartu

2006
20	EE	Kenneth S. Stevens, Florentin Dartu: Algorithms for MIS vector generation and pruning. ICCAD 2006: 408-414
2005
19	EE	Florentin Dartu, Anirudh Devgan, Noel Menezes: Variability modeling and variability-aware design in deep submicron integrated circuits. ACM Great Lakes Symposium on VLSI 2005: 1
18	EE	Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail: Statistical static timing analysis: how simple can we get? DAC 2005: 652-657
17	EE	Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu: Piece-wise approximations of RLCK circuit responses using moment matching. DAC 2005: 927-932
16		Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Expanding the frequency range of AWE via time shifting. ICCAD 2005: 935-938
15	EE	Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Weibull-based analytical waveform model. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1156-1168 (2005)
2004
14	EE	Aseem Agarwal, Florentin Dartu, David Blaauw: Statistical gate delay model considering multiple input switching. DAC 2004: 658-663
13	EE	Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Modeling unbuffered latches for timing analysis. ICCAD 2004: 254-260
2003
12	EE	Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Weibull Based Analytical Waveform Model. ICCAD 2003: 161-168
2002
11	EE	Seung Hoon Choi, Kaushik Roy, Florentin Dartu: Timed pattern generation for noise-on-delay calculation. DAC 2002: 870-873
10	EE	Emrah Acar, Florentin Dartu, Lawrence T. Pileggi: TETA: transistor-level waveform evaluation for timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 605-616 (2002)
1998
9	EE	Florentin Dartu, Lawrence T. Pileggi: TETA: Transistor-Level Engine for Timing Analysis. DAC 1998: 595-598
1997
8	EE	Florentin Dartu, Lawrence T. Pileggi: Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. DAC 1997: 46-51
7		Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi: CMOS Gate Delay Models for General RLC Loading. ICCD 1997: 224-229
1996
6	EE	Florentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi: RC-Interconnect Macromodels for Timing Simulation. DAC 1996: 544-547
5	EE	Bogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi: An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. DAC 1996: 611-616
4	EE	Florentin Dartu, Noel Menezes, Lawrence T. Pileggi: Performance computation for precharacterized CMOS gates with RC loads. IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 544-553 (1996)
1994
3	EE	Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage: A Gate-Delay Model for high-Speed CMOS Circuits. DAC 1994: 576-580
2	EE	Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage: RC interconnect synthesis-a moment fitting approach. ICCAD 1994: 418-425
1993
1		Ion Constatin Tesu, Florentin Dartu: Piecewise Linear Macromodels for Elementary Logic and Fuzzy Circuits. ISCAS 1993: 1718-1721

Coauthor Index

1	Emrah Acar	[10]
2	Aseem Agarwal	[14]
3	Chirayu S. Amin	[12] [13] [15] [16] [17] [18]
4	Ravishankar Arunachalam	[7]
5	David Blaauw (David T. Blaauw)	[14]
6	Seung Hoon Choi	[11]
7	Umakanta Choudhury	[18]
8	Anirudh Devgan	[19]
9	Nagib Hakim	[18]
10	Yehea I. Ismail	[12] [13] [15] [16] [17] [18]
11	Kip Killpack	[18]
12	Noel Menezes	[2] [3] [4] [18] [19]
13	Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage)	[2] [3] [4] [5] [6] [7] [8] [9] [10]
14	Satyamurthy Pullela	[2]
15	Jessica Qian	[3]
16	Kaushik Roy	[11]
17	Ahmed M. Shebaita	[16]
18	Kenneth S. Stevens	[20]
19	Ion Constatin Tesu	[1]
20	Bogdan Tutuianu	[5] [6]

Colors in the list of coauthors