| 2004 |
|---|
| 11 | EE | Jinan Lou,
Wei Chen:
Crosstalk-Aware Placement.
IEEE Design & Test of Computers 21(1): 24-32 (2004) |
| 2002 |
|---|
| 10 | EE | Jinan Lou,
Shashidhar Thakur,
Shankar Krishnamoorthy,
Henry S. Sheng:
Estimating routing congestion using probabilistic analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 32-41 (2002) |
| 9 | EE | Amir H. Salek,
Jinan Lou,
Massoud Pedram:
Hierarchical buffered routing tree generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 554-567 (2002) |
| 2001 |
|---|
| 8 | EE | Jinan Lou,
Shankar Krishnamoorthy,
Henry S. Sheng:
Estimating routing congestion using probabilistic analysis.
ISPD 2001: 112-117 |
| 1999 |
|---|
| 7 | EE | Amir H. Salek,
Jinan Lou,
Massoud Pedram:
MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search.
DAC 1999: 472-478 |
| 6 | EE | Jinan Lou,
Wei Chen,
Massoud Pedram:
Concurrent logic restructuring and placement for timing closure.
ICCAD 1999: 31-36 |
| 5 | EE | Amir H. Salek,
Jinan Lou,
Massoud Pedram:
An integrated logical and physical design flow for deep submicron circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1305-1315 (1999) |
| 1998 |
|---|
| 4 | | Jinan Lou,
Amir H. Salek,
Massoud Pedram:
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits.
ASP-DAC 1998: 295-300 |
| 3 | EE | Amir H. Salek,
Jinan Lou,
Massoud Pedram:
A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together.
DAC 1998: 128-134 |
| 2 | EE | Amir H. Salek,
Jinan Lou,
Massoud Pedram:
A simultaneous routing tree construction and fanout optimization algorithm.
ICCAD 1998: 625-630 |
| 1997 |
|---|
| 1 | EE | Jinan Lou,
Amir H. Salek,
Massoud Pedram:
An exact solution to simultaneous technology mapping and linear placement problem.
ICCAD 1997: 671-675 |
