| 2004 |
|---|
| 9 | EE | Xiaogang Du,
Sudhakar M. Reddy,
Don E. Ross,
Wu-Tung Cheng,
Joseph Rayhawk:
Memory BIST Using ESP.
VTS 2004: 243-248 |
| 2000 |
|---|
| 8 | | Don E. Ross,
Tim Wood,
Grady Giles:
Conversion of small functional test sets of nonscan blocks to scan patterns.
ITC 2000: 691-700 |
| 1995 |
|---|
| 7 | EE | Jawahar Jain,
Dinos Moundanos,
James R. Bitner,
Jacob A. Abraham,
Donald S. Fussell,
Don E. Ross:
Efficient variable ordering and partial representation algorithm.
VLSI Design 1995: 81-86 |
| 6 | EE | Murali M. R. Gala,
Don E. Ross,
Karan L. Watson,
Beena Vasudevan,
Peter Utama:
Built-in self test for C-testable ILA's.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1388-1398 (1995) |
| 1993 |
|---|
| 5 | | Sherif H. K. Embabi,
R. Damodaran,
R. Bhagwan,
Don E. Ross:
An Accurate Delay Model for BiCMOS Gates and Off-chip Drivers.
ISCAS 1993: 1539-1542 |
| 1992 |
|---|
| 4 | EE | M. Ray Mercer,
Rohit Kapur,
Don E. Ross:
Functional Approaches to Generating Orderings for Efficient Symbolic Representations.
DAC 1992: 624-627 |
| 1991 |
|---|
| 3 | EE | Kenneth M. Butler,
Don E. Ross,
Rohit Kapur,
M. Ray Mercer:
Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams.
DAC 1991: 417-420 |
| 2 | EE | Don E. Ross,
Kenneth M. Butler,
M. Ray Mercer:
Exact ordered binary decision diagram size when representing classes of symmetric functions.
J. Electronic Testing 2(3): 243-259 (1991) |
| 1988 |
|---|
| 1 | EE | Rhonda Kay Gaede,
Don E. Ross,
M. Ray Mercer,
Kenneth M. Butler:
CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology.
DAC 1988: 597-600 |
